A Bit-Sequential VLSI "Pixel-Kernel-Processor" For Image Processing

O. R. Hinton; H.-G. Kim

doi:10.1117/12.952282

21 April 1986 A Bit-Sequential VLSI "Pixel-Kernel-Processor" For Image Processing

O. R. Hinton, H.-G. Kim

Proceedings Volume 0596, Architectures and Algorithms for Digital Image Processing III; (1986) https://doi.org/10.1117/12.952282
Event: 1985 International Technical Symposium/Europe, 1985, Cannes, France

Abstract

An architecture for image processing based on a "pixel-kernel-processor" approach is described in detail. The pixels are processed in raster scan order, and it is shown that many of the complexity and data communication problems of cellular-logic-arrays are avoided. By extensive use of pipelining and bit-sequential arithmetic, it is shown that a processor device is readily feasible in current NMOS or CMOS technology. The structure is flexible in that devices may be paralleled up to increase both kernel size and performance, and video throughput rates are readily attainable.

Citation Download Citation

O. R. Hinton and H.-G. Kim "A Bit-Sequential VLSI "Pixel-Kernel-Processor" For Image Processing", Proc. SPIE 0596, Architectures and Algorithms for Digital Image Processing III, (21 April 1986); https://doi.org/10.1117/12.952282

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available