For a device manufacturer, lithography alignment tolerance vs die yield is of major concern. Often device designers will be working off a set of design rules, but the practical are not able to provide such information ahead of time. It is often necessary to obtain it through correlation of alignment keys and end product yields. How accurate these scribe grid keys correlate with the actual circuit yield can make this issue confusing. A new concept of generating this information from die yields has been evaluated with quite promising results.