4 April 1986 Systolic Array Architecture For The Sequential Stack Decoding Algorithm
Author Affiliations +
A very time consuming step in the existing sequential stack decoding algorithm, known as the stack reordering, is shown to be not fully necessary. The algorithm is then modified and restated in a more concise version so that it can be efficiently implemented by a special type of systolic array called systolic priority queue. This scheme is shown to have simple and regular structure as well as high speed for decoding any convolutional codes, including long convolutional codes.
© (1986) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
C. Y. Chang, K. Yao, "Systolic Array Architecture For The Sequential Stack Decoding Algorithm", Proc. SPIE 0696, Advanced Algorithms and Architectures for Signal Processing I, (4 April 1986); doi: 10.1117/12.936893; https://doi.org/10.1117/12.936893


WDM coding for high-speed lightwave systems
Proceedings of SPIE (November 01 1993)
Applications development of the Intel iWarp system
Proceedings of SPIE (March 11 1993)
LDPC OFDM space-time multipath fading channel results
Proceedings of SPIE (July 23 2003)
Concurrent Viterbi Algorithm With Trace-Back
Proceedings of SPIE (April 04 1986)

Back to Top