Systolic Array Architecture For The Sequential Stack Decoding Algorithm

C. Y. Chang; K. Yao

doi:10.1117/12.936893

4 April 1986 Systolic Array Architecture For The Sequential Stack Decoding Algorithm

C. Y. Chang; K. Yao;

Author Affiliations +

Proceedings Volume 0696, Advanced Algorithms and Architectures for Signal Processing I; (1986) https://doi.org/10.1117/12.936893
Event: 30th Annual Technical Symposium, 1986, San Diego, United States

Abstract

A very time consuming step in the existing sequential stack decoding algorithm, known as the stack reordering, is shown to be not fully necessary. The algorithm is then modified and restated in a more concise version so that it can be efficiently implemented by a special type of systolic array called systolic priority queue. This scheme is shown to have simple and regular structure as well as high speed for decoding any convolutional codes, including long convolutional codes.

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C. Y. Chang, K. Yao, "Systolic Array Architecture For The Sequential Stack Decoding Algorithm", Proc. SPIE 0696, Advanced Algorithms and Architectures for Signal Processing I, (4 April 1986); doi: 10.1117/12.936893; https://doi.org/10.1117/12.936893

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