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4 April 1986 The Residue Number System For VLSI Signal Processing
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A new VLSI design method is developed for digital signal processors based on residue number systems and linear systolic arrays. The method breaks large processors into a set of small parallel processors that are interconnected only at the input and the output. Each of the parallel processors is a linear systolic array made up of a set of nearest-neighbor-connected, minimally complex, identical cells. The method has been illustrated by the design of a digital finite impulse response (FIR) filter which is projected for single chip VLSI implementation in 1.25 μm technology to have more than 5 x 1012 gate-Hz/cm2 throughput rate. A proof-of-concept filter has been implemented in 4 micron nMOS by 23 custom chips, each of approximately 20,000 transistor complexity. The filter has a combination of characteristics difficult to achieve with other design techniques--128 fully programmable taps and 136 dB dynamic range--yet it contains only 150,000 gates and has 5 MHz throughput. A fault-tolerant version of the filter provides the error-correction capability of triplication and voting, but it requires a redundancy of only 40%--one-third that required by triplication. In general, an RNS filter with N parallel processing channels can be provided with the fault tolerance of triplication and voting with one-Nth as much redundant hardware. By choosing a systolic architecture that computes outputs in parallel, an amount of fault tolerance can be provided that equals the use of triplication and voting at every stage of the filter.
© (1986) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
B. L. Johnson, E. A. Palo, R. J. Cosentino, and J. J. Vaccaro "The Residue Number System For VLSI Signal Processing", Proc. SPIE 0696, Advanced Algorithms and Architectures for Signal Processing I, (4 April 1986);

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