Paper
23 March 1986 Circulating Packet Threshold Logic To Implement Msd Logic Modules
David L. Flannery, L. Maugh Vail, Steven C. Gustafson
Author Affiliations +
Abstract
Threshold logic element designs in circulating packet form are presented for the implementation of addition and subtraction using modified sign digit (MSD) arithmetic. This arithmetic is attractive for digital optical computing due to its inherent parallelism and pipelining characteristics, which capitalize on natural strengths of optics. To illustrate application of these concepts, a design for CORDIC rotation modules to accomplish the complex Givens rotations required for systolic array QU matrix factorization is presented. This design accomplishes QU factorization using only threshold logic elements and bit-shift operations in a systolic configuration. Although implementable in principle by either electronic or optical means, the design is amenable to optical implementation because it involves high levels of parallelism and interconnections.
© (1986) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
David L. Flannery, L. Maugh Vail, and Steven C. Gustafson "Circulating Packet Threshold Logic To Implement Msd Logic Modules", Proc. SPIE 0698, Real-Time Signal Processing IX, (23 March 1986); https://doi.org/10.1117/12.976271
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KEYWORDS
Logic

Logic devices

Binary data

Signal processing

Computer architecture

Array processing

Computer programming

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