23 March 1986 Design And Vlsi Implementation Of An On-Line Algorithm
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We present a design and its VLSI implementation of a radix-2 on-line algorithm for the basic function Y = AX + B in NMOS technology and discuss its area/time characteristics. The design uses internal pipelining to achieve a short step time of about three gate delays. The on-line delay is 5. The implementation is modular using a 150-transistor bit-slices. We also illustrate the use of the module in implementing a root solver for a polynomial equation.
© (1986) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Dean M. Tullsen, Dean M. Tullsen, Milos D. Ercegovac, Milos D. Ercegovac, } "Design And Vlsi Implementation Of An On-Line Algorithm", Proc. SPIE 0698, Real-Time Signal Processing IX, (23 March 1986); doi: 10.1117/12.976250; https://doi.org/10.1117/12.976250

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