23 March 1986 Digital Optical Linear 3 X 3 Bit Combinatorial Systolic Multiplication Array
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Proceedings Volume 0698, Real-Time Signal Processing IX; (1986); doi: 10.1117/12.976261
Event: 30th Annual Technical Symposium, 1986, San Diego, United States
Abstract
This manuscript represents the second paper in a series of publications describing alternative combinatorial logic based optical computing architectures. Within the first paper titled "Combinatorial Logic Based Optical Computing," justification for combinatorial logic is initially debated through the coupled use of extensive optical interconnects with the natural "and-or-invert" capability of most every optical system.1 This is followed by a simple example of an optical "text" processor, a word and phrase comparitor which can be used for massive text look-up and search. This demonstrates the ability to design a wide range of digital optical architectures capable of performing numerous, if not myriad, sets of digital functions other than mathmatical. The original paper continues to describe a digital optical full adder enhanced by the full global broadcast capability of optics. Finally, a 2 x 2 bit systolic multiplier is described for matrix processing where the limitations of the DMAC algorithm are finally overcome.2-5 The output is thus a full 4 bit binary weighted result.
© (1986) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
P. S. Guilfoyle, W. J. Wiley, "Digital Optical Linear 3 X 3 Bit Combinatorial Systolic Multiplication Array", Proc. SPIE 0698, Real-Time Signal Processing IX, (23 March 1986); doi: 10.1117/12.976261; https://doi.org/10.1117/12.976261
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KEYWORDS
Transducers

Signal processing

Optical computing

Channel projecting optics

Diffraction

Logic

Sensors

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