The need to send Photographic images on Telecommunication network is well established today and more than numerous publications on this subject has been issued. On narrow band channel, typically 64 Kbit/s, known as e.g. B channel on the emerging ISDN, Real Time Still image services like Photovideotex, are within hand reach and largely under studies. One of these studies, funded by C.E.C. (Commission of the European Community) and known as the ESPRIT-PICA Project aims to produce an algorithm capable of compressing a Photovideotex image to less than 1 bit/pel than can be decoded at ISDN data rates. If the network can today, cater for Real Time Still image Services, the coding and decoding complexity of a renowned high compression scheme like A.D.C.T. might still remain the bottleneck of the Real time Implemen-tation. To remedy this situation a new approach of the DCT algorithm has been sought and has led to a very fast implementation of the Forward and Inverse D.C.T. in distributed arithmetic which is furthermore well suited to Integration. The approach is based on the decomposition of the DCT into polynomial products, and the evaluation of the polynomial products by distributed arithmetic. This leads to LSI chip, with a great regularity and testabili-ty. Furthermore, the same structure can be used for FFT computation by the modification of the ROM content of the chip. This architecture is theoritically based on a new formulation of a length - 2N DCT as a cyclic convolu-tion, which is described in the first section of the paper. Other sections will describe the implementation of the D.C.T. using Distributed Arithmetic approach and its evaluation in VLSI.