Translator Disclaimer
25 November 1987 A Systolic Array For Efficient Execution Of The Faddeev Algorithm
Author Affiliations +
The Systolic Processor with a Reconfigurable Interconnection Network of Transputers (SPRINT) is a sixty-four-element multiprocessor developed at Lawrence Livermore National Laboratory to evaluate systolic algorithms and architectures experimentally. The processors are interconnected in a reconfigurable network which can emulate networks such as the two-dimensional mesh, the triangular mesh, the trapezoidal mesh, the tree, and the shuffle-exchange network. The SPRINT's computation capability surpasses its communication capability. Techniques have been developed to perform the Faddeev Algorithm utilizing most of its computing capability by operating on block matrices. These techniques reduce communication bandwidth requirements for a given computation rate and increase efficiency to close to 100%. The Faddeev algorithm calculates the quantity CX+D, where X is the solution to AX=B and where A, B, C and D are given. All quantities are square matrices. Several linear algebra operations such as the matrix-matrix product and matrix inversion can be calculated by loading appropriate values for A, B, C, and D. The Faddeev algorithm is executed on the SPRINT to compare theory with experiment.
© (1987) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
A. J. De Groot, E. M. Johansson, and S. R. Parker "A Systolic Array For Efficient Execution Of The Faddeev Algorithm", Proc. SPIE 0827, Real-Time Signal Processing X, (25 November 1987);


Back to Top