Automatic Design And Partitioning Of VLSI Systolic/Wavefront Arrays

H. Nelis; E. Deprettere; J. Bu

doi:10.1117/12.942041

25 November 1987 Automatic Design And Partitioning Of VLSI Systolic/Wavefront Arrays

H. Nelis; E. Deprettere; J. Bu

Author Affiliations +

Proceedings Volume 0827, Real-Time Signal Processing X; (1987) https://doi.org/10.1117/12.942041
Event: 31st Annual Technical Symposium on Optical and Optoelectronic Applied Sciences and Engineering, 1987, San Diego, CA, United States

Abstract

In this paper, we present a procedure to trans-form algorithms into equivalent regular algorithms. Then, starting from these regular algorithms, we show how to synthesize systolic/wavefront arrays that can be programmed to solve problems of arbitrary size. Buffer memory and control of a resulting array is regular and simple. Also, the through-put of the array is balanced with the I/O speed of the host to which it is to be attached. Methods and tools which are presented are consistent with, and embedded in our hierarchical and interactive flow graph integration system HIFI.

Citation Download Citation

H. Nelis, H. Nelis, E. Deprettere, E. Deprettere, J. Bu, J. Bu, } "Automatic Design And Partitioning Of VLSI Systolic/Wavefront Arrays", Proc. SPIE 0827, Real-Time Signal Processing X, (25 November 1987); doi: 10.1117/12.942041; https://doi.org/10.1117/12.942041

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