1 January 1988 Evaluation Of Multilayer Resists For Submicron Technology
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Abstract
PCM-, trilevel-RIE- and singlelevel-RIE-resist systems are investigated for application in submicron technology. Simulation results of the PCM-technique are compared with experimental results using the K809/PMMA system. Gate and sub-micron contact hole etch results are presented for the Shipley PCM system using PMGI as the planarizing layer. For the trilevel technique using SOG or a-Si as intermediate layer, the loss of linewidth during bottom resist 02-RIE was of main interest. Finally, a dry developing technique, the DESIRE process using the PLASMASK resist, was studied and tested on device wafers.
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Christoph Nolscher, Christoph Nolscher, Gunter Czech, Gunter Czech, Jurgen Karl, Jurgen Karl, Klaus Koller, Klaus Koller, } "Evaluation Of Multilayer Resists For Submicron Technology", Proc. SPIE 0920, Advances in Resist Technology and Processing V, (1 January 1988); doi: 10.1117/12.968345; https://doi.org/10.1117/12.968345
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