A new wafer metrology system, featuring high throughput, automation, and E-beam accuracy has been developed. Novel technologies were integrated into the system in order to meet the stringent requirements of in-process VLSI critical dimension control.

The reduction of integrated circuit dimensions to the submicron range has necessitated the use of low voltage scanning electron microscopy (SEM) for linewidth metrology 1,2. SEM offers advantages of higher resolution and increased depth of focus relative to optical linewidth measurement systems. Low voltage SEM offers a nondestructive method to acquire precise linewidth measurements from features too small for optical systems. In SEM metrology, a primary electron beam traverses the sample surface and the interaction results in a variety of electron signals3. Imaging of wafer topography in the SEM is accomplished by collecting secondary electrons which are emitted from depths of less than about 10 nm of the sample surface. The secondary electron signal is transformed into a video signal as an intensity distribution to be displayed on a CRT. To perform a linewidth measurement, a threshold is selected to determine the distance between the edges of the video profile at that threshold. The threshold technique is critically sensitive to various SEM parameters including the primary electron energy, the beam diameter, and the defocus of the beam4. This sensitivity makes it necessary to calibrate the SEM system after most changes in operating conditions5,6,7. Thus accurate linewidth measurements require an understanding of how the profile and physical dimensions of the feature being measured relate to the video signal. Complications arise because features formed in different materials and on varying substrates result in a variety of video signal profiles. This study was undertaken for the following reasons: *Determine the correlation between low voltage SEM measured linewidth and the physical linewidth of photoresist features on different substrates. *Determine the correlation between low voltage SEM linewidth and physical linewidth for different resist profiles. *Determine the correlation of low voltage SEM linewidth with electrical linewidth measurements performed on polysilicon and aluminum features. *Determine the dependence of low voltage SEM linewidth measurements on wafer tilt and SEM defocus.

The KLA/Holon 2711 is an electron beam based system, using a thermal field emission source, specifically designed for the IC metrology application. Systems such as this are increasingly used in IC production due to decreasing line widths.[1] Accuracy is the major reason to use high resolution e-beam technology for metrology. The system is the first to have a complete keyboard interface which allows for easy and fast operation. Thruput and reliability data are presented. Important column and measurement parameters were optimized to get the best precision and the results are reported. Data is presented which shows the system to be accurate in both its ability to correlate to a cross section standard ("absolute accuracy") and to track the bottom width of a resist feature ("relative accuracy"). (This is a results orientated paper. For a more complete system description please refer to the paper presented last year at this conference by the same authors.)

The need for feature-size measurements on microchips for VLSI and other developing technologies with micrometer and submicrometer dimensions has resulted in using scanning electron microscopes (SEMs) for critical dimension measurements during fabrication. However, good measurement practice requires the ability to accurately predict the observed signal output for any given feature. The model used to predict the output then becomes the basis for measurement algorithms, error analysis, and proper calibration techniques. The SEM, especially for secondary electron imaging and low beam voltages, has lacked the ability to quantitatively predict image waveforms at the 0.01 μm level needed for sub-micrometer dimensional control. This paper describes such a model for SEM imaging and edge detection. A new approach to secondary-electron image modeling has been developed consisting of a surface integral (over the line geometry) of a probability density function which describes the likelihood of a secondary electron being generated by the primary beam and emitted at a given point in space, if that point coincides with the surface of a line. This probability density function can be determined by using either a state-of-the-art Monte Carlo technique or by using a modified diffusion model which is a good approximation to the Monte Carlo method and greatly reduces the computation time. The calculation of the image from this probability density function takes into account edge geometry and shadowing due to nearby edges as well as field effects due to any bias voltage on the electron-detector grid. The Monte Carlo approach takes into account the fact that low energy secondary electrons cannot be produced inside the specimen by a primary or high energy secondary electron after it exits the surface of the specimen. The resulting probability density function which is referred to here as "forward-looking" is, therefore, not a gaussian distribution. An alternate approach to determination of the probability density function uses a modified diffusion model which, although it does not take into account the forward-looking aspect of electron scattering at edges, is shown to approximate edge images well. The diffusion approach has the advantage that calculations can be readily performed on a desktop computer in seconds as compared to hours for Monte Carlo simulations. In addition, it is readily adapted to the development of edge detection algorithms and error analyses.

An annular shape micro channel plate(MCP) placed above a wafer is a detector suited for electron beam (EB) line-width measurement. Acceptance diagrams for secondary electrons and packscattered electrons on the MCP detector were obtained by the surface charge method (SCM) calculation. The secondary electron detection efficiencies on the MCP detector were also obtained from this calculation. By applying adequate bias voltage at the center pipe of the MCP detector, the efficiency is increased to 95%.

A method of stepper lens evaluation has been developed which utilizes a simple resolution test pattern of the type usually supplied with the stepper. Measurements are made using an automated field emission SEM equipped to perform whole wafer non-destructive critical dimension analysis. Measurement data on focus and sizing is then analyzed by a computer program easily run on a small personal computer. Information on reticle sizing errors and wafer flatness may also be included in the analysis to minimize errors.

In an effort to learn more about the nature and distribution in size of particles encountered in device fabrication, we have studied the non destructive inspection performance obtained with standard and low voltage scanning electron microscopes. To simulate particle defects in and on layers, diamond particles with known size were used. This present study proves that the low voltage SEM is an excellent tool to detect and measure very small particle defects on layers but the performance for particles within layers is marginal.

Confocal Laser Scanning Microscopy is becoming an important tool in the quantitative analysis of submicron structures in the field of in-process critical dimension measurements. In addition, this kind of microscopy possesses great potential for applications in automatic defect detection. Special microscope systems for critical dimension measurements have been reported in several areas in semiconductor research and fabrication (1, 2, 3, 4). The technical realization of these systems is based on two different principles: the beam scanning microscopes and the object scanning microscopes. The purpose of this contribution is to present some of the technical details and possibilities of a fully automated beam scanning microscope for VLSI metrology. Furthermore, the first results of an automatic wafer defect inspection system based on the same technology are presented.

This paper compares results obtained with semiconductor metrology systems based upon ultra-violet and visible wavelength confocal microscopy. It is shown that the system is capable of linear metrology of resist features down to 0.5 micron linewidth with low dependence on substrate type. Short term precision of better than 5nm standard deviation can be obtained with this system. Experimental data compares the performance of ultra-violet and visible light versions of the system for resist metrology, showing the benefit of using a wavelength at which the resist is absorbent.

The measurement of critical dimensions (CDs) as small as 0.5 μm is essential to the characterization and control of submicron optical lithography. This paper describes a newly developed system using an ultraviolet laser and the results which have been obtained on various photoresist images, etched patterns, and substrates. A plot of these optical measurements versus SEM measurements shows an offset as expected. However, the data has an excellent linear relation down to below 0.5 um in all the samples above. The excellent results of the resist measurement come from not only the high resolution, but the reduction of the interference effect.

A description of a new product, the first to utilize Coherence Probe Imaging, is given, and application results are presented. In Coherence Probe Imaging, data from an interference microscope is transformed by means of a nonlinear transformation implemented electronically to produce three dimensional images of higher resolution than an ordinary microscope. Because of the parallel nature of the image acquisition, conventional light sources can be used for illumination. Critical dimension or linewidth data analysis is presented. Comparisons to scanning electron microscope measurement are made. Typical linewidth reports are shown. Illustrative reports from the layer to layer misregistration measurement function of the machine is also shown. The coherence probe technique is used to make extended depth of focus pictures and z maps showing topographical detail. Sample images showing these features are shown. Automation features of the machine are also described, such as the automatic wafer alignment system on the machine and the random access robotic wafer handling system.

In recent years, there has been a resurgence of interest in light microscopy One reason is the practical development of confocal scanning optical microscopes (CSOMs). CSOMs image twice the spatial frequencies of a conventional microscope, giving them better transverse resolution.1 In addition, they have a shallower depth of focus, meaning out-of-focus portions of the sample are not imaged; this property makes the CSOM ideal for optical sectioning and profiling.2 In this paper, we will describe a new real-time scanning optical microscope (RSOM) capable of operating at 640 frames per second with 5000 lines in the image. The microscope generates a directly observable color image with different depths displayed as different colors. Our real-time CSOM is based on the real-time tandem scanning optical microscope (TSOM) of Petran.3,4 The microscope, however, uses fewer optical components and is mechanically much simpler and easier to align than currently existing scanning optical microscopes or the TSOM. In addition to its speed and simplicity, the microscope maintains all the advantages of conventional CSOMs. We will also describe a number of add-on systems, such as phase-contrast imaging and dark field imaging which we have developed. Many of these ideas were first tried on a standard mechanically scanned CSOM, with the aim of incorporating them into the RSOM.

Most optical inspection systems are mainly sensitive to the amplitude changes of the light reflected from an object. An example is a scanning optical microscope which uses a detector in the pupil of the objective lens. Another example is a confocal scanning optical microscop 1. Both detection modes however do not measure the phase changes of the light reflected from the object in an easily interpretable way. These phase changes give useful information on the height variations of the object, such as topography and roughness. A very simple and powerful measuring technique called differential phase contrast can be used in scanning optical microscopes to give information on phase objects. Height variations down to 1 nm can be measured with this detection mode. One of the disadvantages of differential phase contrast detection is the fact that structures out of focus give a large modulation of the output signal. Especially on integrated circuits many structures are higher than the focal depth, thus giving blurred images due to out of focus parts of the object. This problem can be overcome when combining differential phase contrast detection with confocal microscopy. Using confocal differential phase contrast detection, phase changes introduced by an object in focus are measured while parts of the object out of focus do not contribute to the signal. The principles of differential phase contrast detection and confocal differential phase contrast detection will be explained. A description of the scanning optical microscope we built will be given. With this microscope we have measured the amplitude and phase of several objects. Both thinner and thicker objects than the focal depth have been measured. Some results are shown which illustrate the advantages of differential phase contrast and confocal differential phase contrast.

Because of their convenience, reliability and moderate cost, it is desirable to extend the measurement capability of optical methods during integrated circuit manufacture as far as theoretically possible into the submicron range. Critical dimensions on photoresist as small as 0.4 micron have been measured with good precision using optical fluorescence microscopy. In addition, using new, recently developed algorithms, etched wafer features below one micron have been measured reliably using briqhtfield techniques.

We show how the speed of scanning in a scanning optical microscope can affect the beam induced current images of semiconducting samples. Experimental and theoretical results showing the effects of scan velocity are presented.

We describe applications of the atomic, magnetic, and electrostatic force microscopes (AFM, MFM and EFM), to metrology problems, especially profiling, magnetic field measurements and potentiometry. The force microscope has many advantages. It is capable of much higher lateral resolution than optics or low-voltage SEM, is nondestructive, operates in air, and does not require samples with special properties, such as electrical conductivity or extreme smoothness. By changing the tip-sample spacing, the speed/resolution tradeoff can be optimized for each application. The basic force probe consists of an L-shaped wire cantilever mounted on a piezoelectric bimorph which serves for terrain following and excitation. The wire is electro-etched to reduce its diameter and form a sharp tip. When the tip and sample are close together, the gradient of the force between them changes the effective spring constant (and thus the resonant frequency of the cantilever; the shift is detected as a changed response to a slightly off-resonance excitation. Force gradients of 10-4 N/m and force increments of 10-13N have been measured in this way, and the current lateral re-solution is 50Å; there seems to be no fundamental impediment to achieving atomic resolution. The electrostatic force microscope is an AFM with a voltage applied to the tip. It makes possible potentiometry through nonconducting passivation layers. The magnetic force microscope (MFM) is very similar. It uses a steel wire tip to make magnetic images with a lateral resolution of better than 1000 A. which we hope to improve to 100 A. We present data illustrating usefulness of all these techniques in metrology problems.

The characterization of photolithographic resolution, proximity-imaging effects, topographic dependence, side-wall spacers, and stacked-gate etch is greatly facilitated through the use of microelectronic test structures. The test modules required were specifically designed to mimick typical linewidth structures that occur as a result of integrated circuit processing. The modules were designed into a generic test reticle set. The reticle set has been implemented on ASM, GCA, Nikon, and Ultratech Steppers. This paper describes the test structures, the measurement sequences, and presents examples of results to demonstrate the versatility and application of this design.

A special technique to electrically measure submicrometer isolated features is described. By incorporating a large number of features in a single test structure, a gain in precision better than 3 nm can be achieved. The interpreted contact hole diameter as well as the area of the isolated features were found to be very accurate. The special test pattern, an analytic expression for interpretation of the results, and hole size data from a variety of exposure dosages are included.

A confocal scanning laser microscope (CSLM) has been used to study a variety of oxide isolation techniques including the LOCOS, S-LOCOS, SWAMI, and M-SWAMI structures. The focal plane sensitivity of the confocal microscope was used to deconvolve effects due to refraction, reflection, and interference of 488nm light propagating in these structures. Elementary optical theory due to Fraunhofer and Fizeau was used to rationalize the data and to permit correlation with physical profiles in both the lateral and vertical directions. We found that considerable enhancement of the instrumental precision could be obtained by adjusting the CSLM to operate at 8000X or greater magnification and by using a saturation threshold technique to acquire focal plane data. The signal-to-noise limited measurement capablity of the system appears to be about 0.07μm with standard deviations of 10%. The standard error of the mean over 49 linescan measurements is about one nanometer.

This paper describes a methodology based on advanced metrology to quantify the overlay performance of individual wafer steppers and a means to optimize their matching. Use of accurate two point through the lens alignment directly referenced to the reticle and a three axis interferometrically controlled X-Y-0 stage permits full characterisation of the individual machine overlay errors. With the help of parameters determined in an extended metrology model of the microlithographic lens distortions and the wafer stage grid distortions one can automatically adjust corresponding machine servo-mechanisms for optimum matching. The model can be used to calculate and predict the systematic errors between random pairs of machines rather thav having to directly measure all pairs, so ensuring efficient, high quality matching. Results of an eight machine matching experiment demonstrating the model's validity and effective use on PAS 2500 wafer steppers are described.

Alignment and setup of lighography processes has largely been conducted on special test wafers. Actual product level optimization has been limited to manual techniques such as optical verniers. This is especially time consuming and prone to inconsistencies when the registration characteristics of lithographic systems are being measured. One key factor obstructing the use of automated metrology equipment on product level wafers is the inability to discern reliably, metrology features from the background noise and variations in optical registration signals. This is often the case for metal levels such as aluminum and tungsten. This paper discusses methods for enhancement of typical registration signals obtained from difficult semiconductor process levels. Brightfield and darkfield registration signals are obtained using a microscope and a 1024 element linear photodiode array. These signals are then digitized and stored on the hard disk of a computer. The techniques utilized include amplitude selective and adaptive and non-adaptive frequency domain filtering techniques. The effect of each of these techniques upon calculated registration values is analyzed by determining the positional variation of the center location of a two line registration feature. Plots of raw and processed signals obtained are presented as are plots of the power spectral density of ideal metrology feature signal and noise patterns. It is concluded that the proper application of digital signal processing (DSP) techniques to problematic optical registration signals greatly enhances the applicability of automated optical registration measurement techniques to difficult semiconductor process levels.

A comprehensive geometrical approach is presented for the least-squares analysis of overlay distortion patterns into useful, physically meaningful systematic distortion subpatterns and an essentially non-systematic residue. A scheme of generally useful distortion sub-patterns is presented in graphic and algorithmic form; some of these sub-patterns are additions to those already in widespread use. A graphic and geometric approach is emphasized rather than an algebraic or statistical approach, and an example illustrates the value in utilizing the pattern-detecting ability of the eye-brain system. The conditions are described under which different distortion sub-patterns may interact, possibly leading to misleading or erroneous conclusions about the types and amounts of different distortions present. Examples of typical interaction situations are given, and recommendations are made for analytic procedures to avoid misinterpretation. It is noted that the lower-order distortion patterns preserve straight-line linearity, but that higher-order distortion may result in straight lines becoming curved. The principle of least-squares analysis is outlined and a simple polynomial data-fitting example is used to illustrate the method. Algorithms are presented for least-squares distortion analysis of overlay patterns, and an APL2 program is given to show how this may easily be implemented on a digital computer. The appendix extends the treatment to cases where small-angle approximation is not permissible.

This paper addresses the task of finding the source of defects that cause die failure at sort on semiconductor wafers. To do this, one must be able to determine defect type and density, in process, in order to determine where in the manufacturing process they are being created. Two methods have been commonly used. First is operator performed inspection of product or test wafers using a microscope. The second is short loop experiments using electrical test structures. Each of these methods have significant limitations when used for engineering analysis on VLSI technologies. Data generated by operator performed inspections show lack of reproducibility and large variations from operator to operator. Also, operator sensitivity declines to very low levels for defect sizes approaching linewidths in current semiconductor technologies. Electrical test structures require a conductive thin film to be patterned and etched. To get finer resolution of the section of the process causing a defect, indirect methods are required. This greatly constrains the options for experimental procedures. Because of the limitations on the methods described so far, defect reduction projects have been difficult, time consuming and prone to failure due to the difficulty of identifying the source of defects. Automated defect inspection, using the KLA-2020 automated wafer inspector, addresses these problems. This results in greatly increased efficiency and success rate. Presented in this paper is a discussion of the capabilities of automated defect inspection as compared to operator performed inspections and electrical test structure based short loop experiments. Also, a defect reduction methodology utilizing automated inspection will be described by presenting an actual example of its application. The methodology consists of using standard problem solving and experiment design techniques to isolate and solve major defect mechanisms. The example presented describes a series of short loop experiments using data generated by the KLA-2020 which successively narrowed down the portion of the process responsible. The problem was solved and a corresponding yield increase was seen.

Defect control in a VLSI production facility is a critical activity for establishing stability and improvement in final die yield. A key aspect of any defect control program is visual inspection of product wafers during their manufacture. Traditionally this has been executed by operators. However, a visual inspection program utilizing automated defect detection equipment has been developed and will be described in this paper. The program places emphasis on monitoring and detecting defects as they occur. The bulk of the inspections are done on critical layers (i.e. layers with a high density of printed and etched patterns) as they will be most susceptible to yield loss. A highly controlled classification system along with proper training of operators is used to maintain the integrity of the collected defect data. A flexible data base, in which the defect data is entered, is used to maximize the analysis techniques that can be applied with this inspection program. Finally, examples of successful application of the program will be described.

Yield maintenance and improvement is a major area of concern in any integrated circuit manufacturing operation. A major aspect of this concern is controlling and reducing defect density. Obviously, large defect excursions must be immediately addressed in order to maintain yield levels. However, to enhance yields, the subtle defect mechanisms must be reduced or eliminated as well. In-line process control inspections are effective for detecting large variations in the defect density on a real time basis. Examples of in-line inspection strategies include after develop or after etch inspections. They are usually effective for detecting when a particular process segment has gone out of control. However, when a process is running normally, there exists a background defect density that is generally not resolved by in-line process control inspections. The inspection strategies that are frequently used to monitor the background defect density are offline inspections. Offline inspections are used to identify the magnitude and characteristics of the background defect density. These inspections sample larger areas of product wafers than the in-line inspections to allow identification of the defect generating mechanisms that normally occur in the process. They are used to construct a database over a period of time so that trends may be studied. This information enables engineering efforts to be focused on the mechanisms that have the greatest impact on device yield. Once trouble spots in the process are identified, the data base supplies the information needed to isolate and solve them. The key aspect to the entire program is to utilize a reliable data gathering mechanism coupled with a flexible information processing system. This paper describes one method of reducing the background defect density using automated wafer inspection and analysis. The tools used in this evaluation were the KLA 2020 Wafer Inspector, KLA Utility Terminal (KLAUT), and a new software package developed by KLA called "Product Wafer Defect Audit" (PWDA). Automating the wafer inspection task has several advantages over a manual inspection. Among these are consistency of defect capture over time and consistency of sample size. Additional information such as exact location, size, and classifications is retained for each defect found. The software package, PWDA, automatically maintains a database of this defect information. This database allows quick retrieval and manipulation of the data in a variety of ways. The use of PWDA software coupled with auto-matic inspection for an offline inspection program in a fab environment is discussed. This includes examples of setting up and collecting a database, evaluation of the data, and the actions taken to decrease the background defect density level.

Although the VLSI products produced in our manufacturing lines are mostly designed with 1 micron geometries, we expect the majority of products will shift to sub-micron design very soon. This article discusses results of our experiments to releaf human operators from the already difficult visual inspection tasks with a fully automated equipment. We have two groups of visual inspection tasks necessary on the VLSI manufacturing floor. One is Engineering Analysis and the other is in-line monitor, or Product Wafer Auditing. The former, Engineering Analysis, demands a variety of different measurements and inspections, such as line width, contact area, multilayer alignment precision and defect density. On the otherhand, Product Wafer Auditing, will need only one or two such functions per mo-nitoring point in the process, but will use the function more extensively, continuously, and repeatedly. In the manufacturing environment, where the ever pressing demand to increase yield is para-mount, it is crucial to reduce defect finding and analysing time. For that purpose, we need higher speed and accuracy for production wafer inspection than can be obtained with human inspectors. In this context, our experience on the KLA-2020, fully automated wafer inspection equipment has proven to be truely beneficial in the area of the following five different cases of evaluation of the KLA-2020, conducted in our plant. Case: 1. Visual inspection of the VLSI production wafer after aluminum dry-etching was studied in comparison with human operators. The result is that not only was the KLA-2020 much more thorough in detecting defects but also was much faster than any of the operators, by far. Case: 2. We applied the KLA-2020 to identify the cause of die, lost at probe test. We traced the killer defect, which was originated from the reticle. KLA-2020 is effective in reticle qualification. Case: 3. We found that the line-width instruments based upon laser scatterology cannot properly measure most of the dense 1 micron geometry of our VLSI devices. However, the KLA-2020 has provided excellent data of such Case: 4. During the course of process development, where the objective was to improve the LW uniformity within a production wafer, we found the efficiency and accuracy of the KLA-2020 were so good that the objective was met successfully in a very short time. In addition, the yield was improved remarkably. Case: 5. There have been no practical and simple methods to measure a small area in a pro-duction VLSI wafer. We will show the experimental results of measuring the area of contact holes in dropouts using the KLA-2020.

Although some control techniques such as Shewhart and CUSUM Control Charts are not new, their application in industry for process control is relatively new. In recent years manufacturing industries have begun to discover and appreciate the power and efficiency of statistical process control techniques. These charts have been successfully used in some areas and have created confusion in others. The confusion is normally due to incorrect application of the methods and lack of sufficient understanding of the theory and assumptions underlying these charts. One of the important assumptions in using Shewhart and CUSUM charts is that the individual measurements are statistically independent. In many industrial situations this assumption is not valid. Namely, the measurements are correlated. As a result the application of the above techniques ends in incorrect conclusions and hence, confusion. The purpose of this paper is to discuss appropriate methods for dealing with these situations. Time series modeling will be discussed. It will be shown how the correlations in data can be used for more precisely predicting and controlling a process.

The need to control and reduce the variability and to center the mean of certain critical parametric device properties in a mulitple product manufacturing line is directly dependent on identifying and controlling the sources of variability in critical dimensions (CD's) in wafer processing. This requires the development of a low cost, statistically valid, simple, and flexible system for data collection, analysis, and real time feedback. Of particular interest in a CMOS process is the sensitivity of the effective channel lengths (Leff) to the post-etch polysilicon linewidth. This paper describes the application of a statistical process control based measurement and response system at four points in the polysilicon photolithography and etch process. The system monitors and directs processing through photo and etch using multiple pieces of coat, projection align, develop, measurement, and etch equipment. With the ability to identify variability contributions from independent process steps, designed statistical experiments (using Design of Experiment (DOX) and Response Surface Method (RSM) techniques) were performed to provide optimization of measurement, coat, develop, exposure, and etch processes. Use of this system has resulted in greatly reduced photoresist rework rate, higher throughput at both align/expose and etch due to reduced set-up time, lower inventory levels (thus reduced cycle times), tighter control of the distribution of post-etch CD's and the ability to position that distribution (resulting in lower scrap rates at this point and tighter speed distributions), and ultimately die yield increases. Equipment and personnel requirements have been reduced. Initial implementation resulted in a 40% reduction in post CD variability for the polysilicon process. These techniques have now been expanded to cover all process levels where critical dimension control is strongly related to product performance.

A data summation method is described that employs summary statistics that are relatively insensitive ("robust") to the presence of spurious observations ("outliers"). The method is quick; it is accurate both with and without outliers present; and it is simple for users to understand. It is then shown that these summary statistics can be used to construct variance component estimators, key tools in process improvement and control. The estimators presented are simpler than the conventional variance component estimators and have significantly smaller data storage requirements.

Device design rules now approach 0.5μm geometries. Process complexities and the performance of conventional equipment necessitate a more sophisticated technique for process optimization. Statistically designed experiments (SDE) and response surface analyses have, to a limited extent, addressed this need, but have fallen short in their ability to handle several responses simultaneously. Recent articles have failed to include realistic concerns such as product throughput or materials consumption. This paper describes an efficient approach to simultaneously optimize several positive lithographic properties and industrial concerns. Process parameters such as 1) soft bake temperature, 2) focus offset, 3) exposure energy, 4) develop process, and 5) developer temperature were varied and investigated using full factorial statistical methods. The lithographic performance of a resist and developer system, whose chemistry was designed specifically for high resolution, zero bias submicron imaging, was characterized. CD uniformity, focus latitude, exposure latitude and throughput were modeled via response surface methodology, and then optimized according to the described technique. Also, a desirability function and an equipment monitoring system were considered and employed. The utility of this technique lies in the definition of conditions wherein the optimum process control and product flow are achieved simultaneously. Typically, a response surface graphically represents the effect of two variables. The described technique effectively considers many variables to establish a process window. Analysis of the full factorial design, with star and center points, was used to build individual response surfaces. The mathematical combination using linear algebraic techniques of several response surfaces is a novel approach to effectively describe the process window. The lithographic process, optimized by the described experimental techniques, exhibited wide latitude. This, coupled with equipment SQC, provided a reliable submicron lithographic process. Equipment capabilities were quantified and consistent performance reported as important factors in total process control. The resultant optimized process window was depicted by engineering data and design space centerpoints were characterized by scanning electron micrographs.

Two expert systems for photolithography are discussed and compared. The systems are found to be beneficial to both engineers and technicians. Important implementation issues are presented.

What capability am I buying with a new stepper purchase? Do I know if the stepper is optimally setup? How is the stepper performance sustained over time? A lithographer is constantly struggling to find answers to these questions. All of the existing metrology tools for stepper characterization are dependent on the resist process, and sometimes further process steps . Measured results are really the combined effects of all the process steps involved and this can change over time, making interpretation of stepper characteristics confusing and often difficult. The Stepper Image Monitor(SIM), a tool that measures stepper performance in real time, completely independent of the resist process, provides the lithography engineer with a fast, precise measurement technique for stepper performance evaluation in three lithography environments: 1. Development 2. Pilot line 3. Production The presentation will include a discussion of how the Stepper Image Monitor(SIM) is used in each one of these lithography environments. For lithography development, stepper parameters such as contrast across the lens field, field curvature, and useable depth of focus(DOF) are measured and examples of measured results are presented. The precision in determining best focus using the SIM provides practical applications for routine focus monitor in the pilot line and in the production environment.

Submicron contact holes in 1.5 μm resist have been characterized using direct SEM measurement and using hole transfer into polysilicon by reactive ion etching. The performance of these measurement techniques is examined as well as the full-field performance of three g-line reduction lenses with numerical apertures equal to .35, .42, and .45. This performance includes resist slope and shape for contacts from 0.7 to 1.2 m in size, reproduced with optimized process and exposure.

Experimental tests were conducted on the hot plate of a 4-inch single-wafer baking oven in order to characterize the dynamics of the wafer temperature during baking, and a factorial experiment was carried out to investigate the significance of these thermal effects on photolithography performance. The purpose was to quantify the effect of temperature overshoot on the critical dimensions, the resist photosensitivity value, and the film thickness, which are the three most significant photolithography outputs. The experimental results indicate that the baking ovens commonly exhibit temperature overshoot by exceeding the prescribed processing temperature. Levels of overshoot of 3°C and 4°C at both the soft-bake and post-exposure bake steps are responsible for statistically significant deviations in critical dimensions and in photosensitivity, with respect to a reference population of films processed under controlled temperature overshoots of 1°C or less. A temperature overshoot of 3°C in the soft-bake cause a small, but statistically significant, increase in CD of 0.011 pm, an increase in ET of 7.5 msec, and a thinning. in resist thickness of 78A. Also, an overshoot of 4°C or greater at post-exposure bake causes an increase in CD's of 0.024 pm, and an increase in ET of 17.5 msec. Further, if overshoots of 3°C or greater at both SB and at PEB occur, then the total CD mean shift is 0.035 μm and the ET mean shift is 25 msec. These output deviations produce a loss in process capability quantitatively measured by the reduction of the process capability index Cpk.

This paper describes an experimental method which led to a 1.2 micron polysilicon process with both a zero bias and near zero micron critical dimension shift over polysilicon topography. These results were attained using a single layer positive photoresist process and a 10X reduction stepper with a 0.28 NA/0.7 partial coherence factor/436nm lens system. The two phase experimental method used in this work included a pretargeting experiment followed by a three variable response surface analysis. In the pretargeting experiment, a standing wave curve over polysilicon steps was generated to find areas of converging exposure thresholds relative to changing resist thickness at the top and bottom of topography. This was done, so that later work, in this study, examined a suitable range of resist thicknesses which did not exhibit photospeed divergence resulting from thickness variations near a step causing improperly balanced standing wave conditions. The final phase of this method included a three level, three variable experimental design, where resist thickness, soft bake time and temperature were chosen as the initial critical parameters to be studied. The quadratic model used in this process optimization required a minimum of three levels to ascertain the curvilinear effects of the process. Initial optimization was done using the previously published function. P(X(1), X(2)...) = TIF(i) i=0 This function represents an overall optimization as defined by the product of normalized signal-to-noise ratios, F(i), for the set of responses for the process variables X(1), X(2) studied.1 In this work, the three responses monitored were linewidth shift over topography at 1.2 micron sizing, energy to size a 1.2 micron target, and lastly, the exposure latitude as defined by the tangent of the linewidth versus exposure curve at the 1.2 micron sizing target. Experimentally, pretargeting work was done by coating topographical polysilicon wafers with resist at varying spin speeds, hot plate baking, then exposing using a serpentine open-frame exposure matrix array. After track development, wafers were visually inspected and the minimum energy to clear the resist off the top and bottom of critical topography was monitored. Spin speeds which yielded best photospeed convergence over the polysilicon steps were then chosen for subsequent experimental design work. To do this work, nineteen polysilicon wafers with topography were coated and baked under varying randomized bake and resist thickness conditions. Each wafer was then patterned with five different exposure levels centered around the energy to size the 1.2 micron target sizing, at approximately 2.4 ET units.2 Then linewidth measurements in a CD cell, and top and bottom of a step were made using a SEM. Finally, after determining response values for each test element, process modeling and optimization was done using E-Chip.1, 3 In this study, the effect of resist thickness and soft bake conditions on linewidth control over relief surfaces is examined and a method for minimizing the degree of these effects is discussed. Also, the method is reviewed and recommendations for general use are made.

In most fully utilized integrated circuit (IC) production facilities, profit is very closely linked with yield. In even the most controlled manufacturing environments, defects due to foreign material are a still major contributor to yield loss. Ideally, an IC manufacturer will have ample engineering resources to address any problem that arises. In the real world, staffing limitations require that some tasks must be left undone and potential benefits left unrealized. Therefore, it is important to prioritize problems in a manner that will give the maximum benefit to the manufacturer. When offered a smorgasbord of problems to solve, most people (engineers included) will start with what is most interesting or the most comfortable to work on. By providing a system that accurately predicts the impact of a wide variety of defect types, a rational method of prioritizing engineering effort can be made. To that effect, a program was developed to determine and rank the major yield detractors in a mixed analog/digital FET manufacturing line. The two classical methods of determining yield detractors are chip failure analysis and defect monitoring on drop in test die. Both of these methods have short comings: 1) Chip failure analysis is painstaking and very time consuming. As a result, the sample size is very small. 2) Drop in test die are usually designed for device parametric analysis rather than defect analysis. To provide enough wafer real estate to do meaningful defect analysis would render the wafer worthless for production. To avoid these problems, a defect monitor was designed that provided enough area to detect defects at the same rate or better than the NMOS product die whose yield was to be optimized. The defect monitor was comprehensive and electrically testable using such equipment as the Prometrix LM25 and other digital testers. This enabled the quick accumulation of data which could be handled statistically and mapped individually. By scaling the defect densities found on the monitors to the known sensitivities of the product wafer, the defect types were ranked by defect limiting yield. (Limiting yield is the resultant product yield if there were no other failure mechanisms other than the type being considered.) These results were then compared to the product failure analysis results to verify that the monitor was finding the same types of defects in the same proportion which were troubling our product. Finally, the major defect types were isolated and reduced using the short loop capability of the monitor.

Reduction steppers require the performance of several diagnostic tests to ensure that their performance meets product specifications. This is no less important at periodic inspections, than it was at the time of initial equipment acceptance. We have implemented an automated monitoring program in which stage stepping precision, array orthogonality, reticle rotation, magnification control, lens distortion, global alignment accuracy, field-by-field alignment accuracy, enhanced global alignment accuracy and resolution are inspected weekly as a part of our preventive maintenance program. With automated data collection, this task takes approximately four hours per machine per week. The results are obtained much faster and more accurately than could be done by manual data collection. Thus the implementation of an automated reduction stepper performance monitor within our manufacturing facility has increased our control over stepper parametric monitoring and has allowed us to utilize our technical resources more efficiently.

Differences between puddle, immersion, and spray development were discussed. Issues affecting submicron profiles were characterized in detail with the aid of both computationally and experimentally generated 0.6 micron (g) profiles. Dissolution rate data for various processes were compared. Modifications to a Perkin-Elmer Development Rate Monitor (DRM) were made to obtain the dissolution rate data; 700nm illumination was used in place of the standard 633nm illumination in order to reduce signal attenuation for low agitation development processes, and the development stage was adapted for use with track processes (puddle). Time and spatial variations in developer temperature accounted for most observed differences between puddle developed and immersion developed profiles. A 3°C drop in the puddle temperature during the course of development produced a substantial alteration in resist profile. Variations in across wafer temperature account for most across wafer critical dimension (CD) variations in puddle processes. No substantial developer depletion effects were observed for single puddle processes. Controlled agitation in immersion development was seen to simultaneously increase photosensitivity and wall angle over non-agitated immersion development.

An optical linewidth measurement station for quality control of wafer production with respect to critical dimension and overlay registration measurements is described. An automatic wafer handler with slit scan photometer, fast scanning stage and pattern align ment module provide fast lot throughput with minimal contamination. A personal computer controls the system and stores measurement recipes and data Linewidths are extracted from high resolution optical intensity profiles using various line edge definitions. Automatic run data on a nominally 0.8 um wide and 2 um high Y-shaped structure of a stepped test pattern for various process levels such as resist on nitride, resist on metal and resist on silicide, are presented to demanstrate instrument positioning and measurement repeatability. The effect of a defined interlayer focus variation (steps from top to bottom of a structure) with a high speed focusing device is correlated to the measurenent results: Data from different types of measuring instruments is compared by linear regression analysis.

The use of S.E.M. for Critical Dimensions is increasing with the need for measurements of less than 1 micron linewidth. This technique is so tedious that it is only acceptable if the measurements can be made in automatic mode. Therefore many difficulties appear such as charge effects which can lead to results containing a few false measurements. In the first method called Signal Recognition method the features of the extreme transitions determined in a preliminary calibration experiment are retained. To attenuate the noise and improve the speed of the treatment only a reduced number of points of the electron profile are taken into account. Thus the measurement uses a threshold zone to take into account the main points of the transition on the actual profile. The previous method must be adjusted for each new layer. Therefore another method was found which uses signal processing on the electron profile and is independent of the layers. The charges effects are attenuated by filtering the spatial frequencies and all the information contained in the edge transitions is taken into consideration. No precise settings of threshold are therefore needed In both cases these methods provide reliable measurements which allow the S.E.M. to be used as a routine metrology tool.

A confocal color laser microscope which utilizes a three color laser light source (Red: He-Ne, Green: Ar, Blue: Ar) has been developed and is finding useful applications in the semiconductor field. The color laser microscope, when compared to a conventional microscope, offers superior color separation, higher resolution, and sharper contrast. Recently some new functions including a Focus Scan Memory, a Surface Profile Measurement System, a Critical Dimension Measurement system (CD) and an Optical Beam Induced Current Function (OBIC) have been developed for the color laser microscope. This paper will discuss these new features.

A new Line Width Standard has been developed. It is a physical specimen consisting of calibrated lines and spaces patterned in metal and dielectric layers on a silicon substrate. The standard is for calibration of reflected light measurement systems. The Line Width Standard is designed such that the optical profile of the standard can be very nearly matched to the optical profile of the specimen the user wants to measure. The calibration of the Line Width Standard is based on first principles of physics and is therefore a primary standard. A special measurement system based on an optical scanning microscope developed at the National Bureau of Standards was built to calibrate the line and space dimensions.

Recent advancements in Hewlett-Packard laser interferometers has made it possible to achieve displacement measurements with a repeatability in the tens of nanometers. This will be of key importance in achieving the submicron geometries in future integrated circuits. This measurement repeatability is achieved by the use of two new products that significantly reduce the major error components of the interferometer system. Before discussing the details of these products, an account is given on how to analyze the measurement repeatability of a laser interferometer system. Each component of the system repeatability budget are discussed. From this analysis it is observed that the most significant error components in this budget are due to atmospheric affects and the thermal drift of the optics. The affects of these errors have been reduced on the Hewlett-Packard system by the use of Wavelength Tracking Compensation and a new high stability interferometer.

This paper discusses INMOS UK's incoming Q.A. procedure for reticle overlay. The technique is based on an electrical differential linewidth test structure, known as a Three Leg Stickman, for measuring misalignment. This structure Is placed at four symmetric positions outside of the datafield of a reticle. When printed on test wafers it allows misalignments to be measured to a repeatabilty of 10nm and an accuracy of better than 20nm across a 20mm printed reticle frame. The paper discusses how the structure was optimised and shows that ±5ppm reticle overlay can be achieved with reticles written on a Varian VLS-40 E-beam system on Borosilicate glass. The technique also provides a variety of other information on stepper performance and has been used as part of an evaluation of the accuracy of commercial optical metrology systems.

A new approach to defect detection and classification in VLSI circuit pattern inspection is described, which employs the Euler number of a local image as a feature. Defect classification rules represented with the sum and diffierence of two Euler numbers for a local image and its complement are derived, and additional rules to eliminate false detections from acceptable edge roughness are introduced. Simulation results for real image data are also presented.

An improved SEM technique to determine MOS transistor effective channel length is described. The technique utilizes two different chemical etchants under strong illumination to selectively stain/etch the doped regions of the device. Comparison of the SEM measurements to data provided by two different electrical measurement methods shows good agreement (within 0.1 μm).

Process windows have shrunk dramatically with the advent of micron and submicron processes in semiconductor manufacturing. Because of this trend, photospeed testing has become an especially critical aspect of photoresist quality control. The purpose of this paper is to describe and evaluate and test methods which can be used by a manufacturer to qualify resist lots. In addition, the applications and benefits of Statistical Quality Control and photospeed certification programs are discussed.