A photolithography for 0.5um feature size was studied. For this experiment a g-line Stepper with a lox lens of 0.6 numerical aperture (N.A.) and 5mm square field size was used. Profiles of both a single layer resist and a trilayer resist were investigated by caking SEM photographs. This process was applied to the fabrication of silicon microwave bipolar transistors. In conventional photoresist processes, 0.45um line and space were resolvable for the photoresist thickness of 1.2um, and the cross sectional profile of the resist was rectangular. The focus depth for 0.5um pattern was ±0.2~0.4um and depended on resist. The 0.5um patterns were uniformly resolved in the field. A 0.5um pattern with 0.5um step height could be resolved. The rectangularity of the resist cross section was strongly dependent on resist properties. The trilayer resist with the feature size of 0.4um line and space was achieved. We Found that the focus depth of the trilayer resist process was ±0.6um and twice as much as that of the conventional single layer resist process. This is because even poor profile of top layer resist was useful for making good rectangular profile of bottom layer resist. As a result, more focus margin could be obtained for the trilayer resist. The same result of focus depth was obtained in the case of 0.5um step height. On 1.0um step height, though 0.5um line and space could be separated, it could not be applied for practical use due to the fluctuation of demensions. This is because bottom layer resist could not form 1 flat surface. Contrast Enhancement Lithography (CEL) process was applied, but no improvement of resolution was obtained. A silicon microwave transistor with minimum size of 0.5um was fabricated using this Stepper. The trilayer resist was applied for the metallization lithography. For 0.5um rule lithography except metallization, the conventional single layer resist process was ased and we made the surface of the wafers as flat as possible. The yield of 0.5um pattern variation less than +0.05um was 60% in a wafer, however some patterns were not resolved. The poor patterns were formed due to the poor flatness of the wafers. Correlation between the flatness of the wafers and the pattern resolution was obtained. Required specification of Local Thickness Variation (LTV) was estimated for single layer and trilayer resist processes, respectively.