14 December 1988 Whole-Field Residual Stress Measurements In Silicon Wafers During Integrated Circuit Fabrication
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Proceedings Volume 0955, Industrial Laser Interferometry II; (1988) https://doi.org/10.1117/12.947660
Event: SPIE International Symposium on Optical Engineering and Industrial Sensing for Advance Manufacturing Technologies, 1988, Dearborn, MI, United States
Abstract
An optical method is proposed which generates the two-dimensional out-of-plane partial contours of silicon wafers and requires only a single numerical differentiation to compute the whole-field residual stress distribution. The optical arrangement for the method requires the use of either a linear or a crossed grating and two large lenses. At the recording stage, this arrangement results in an instantaneous reconstruction of the grating lines into the contours of partial slopes of the wafer. Visual inspection of these contours allows an immediate qualitative evaluation of the local stress variations. Contours with good contrast are obtained even for wafers with circuits printed on them. The partial curvatures are obtained by numerically differentiating the slope contour data. The wafer is modelled as a composite structure consisting of a thin film deposited on the silicon substrate. The two-dimensional residual stress distributions in the film and the substrate are obtained from the curvatures using a plate bending theory approach. The proposed method was used to follow the development of residual stresses in silicon wafers during integrated circuit fabrication using an n-MOS silicon gate process. It was found that the local oxidation step introduced maximum residual stresses whereas the metalization step had a small counter influence on the stresses. The local residual stress variations were enough to cause the conventional average measure to be in error by a factor of two even for wafers without stacking faults. This method can be a valuable tool for a fast and accurate quality control of incoming and outgoing wafers, and can provide useful guidelines for wafer fabrication process research.
© (1988) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Raghunath P. Khetan, Raghunath P. Khetan, Kailash C. Jain, Kailash C. Jain, } "Whole-Field Residual Stress Measurements In Silicon Wafers During Integrated Circuit Fabrication", Proc. SPIE 0955, Industrial Laser Interferometry II, (14 December 1988); doi: 10.1117/12.947660; https://doi.org/10.1117/12.947660
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