23 February 1988 A Highly Reconfigurable Array Of Powerful Processors
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This paper presents a highly reconfigurable architecture for two-dimensional (2D) arrays of powerful processors. Because of its high degree of reconfigurability the architecture can provide fault tolerance with efficient array utilization and support application programs requiring different interconnection structures. The proposed 2D array incorporates a flexible interconnection network using a mechanism called virtual channels. Ideally, the interconnection mechanism of a reconfigurable array would be infinitely reliable and flexible. Our evaluation results, based on the simulation of real programs for an array of Warp processors (a powerful processor developed at Carnegie Mellon and manufactured by GE), show that we can approach this goal with a modestly complex switch design.
© (1988) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
R. Cohn, R. Cohn, H. T. Kung, H. T. Kung, O. Menzilcioglu, O. Menzilcioglu, S. W. Song, S. W. Song, } "A Highly Reconfigurable Array Of Powerful Processors", Proc. SPIE 0975, Advanced Algorithms and Architectures for Signal Processing III, (23 February 1988); doi: 10.1117/12.948516; https://doi.org/10.1117/12.948516

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