Many important problems in real-time image processing involve both high computational requirements and a complex and substantial data flow. The system designer must weigh the difficulty of partitioning the problem to fit onto commercial hardware versus the expense of embedding the algorithm in an ASIC or an ASIC chip set subject to constraints on device and pin count, data path complexity, etc. A consistent system architecture evaluation methodology and tool set for addressing the implementation of such problems in a combination of software and hardware is sorely needed; this paper presents first steps in that direction. In order to demonstrate a typical set of trade-offs, we cite the pan-zoom-rotate (PZR) problem, i.e., the problem of processing an input scene for viewing at arbitrary translation, rotation, and magnification in real time. This problem requires both a very high computational rate and high image data bandwidth; sophisticated memory addressing and management are also needed, as access patterns to the input data are non-trivial. We are using the Architecture Design and Assessment System (ADAS) and a number of other tools to determine and model the computational and data flow constraints of this problem and to experiment with different partitioning strategies for the algorithms. We describe the methods we have used to determine these constraints, why these constraints rule out implementation via commercial DSP chips, and how our architecture assessment tools have been used to develop candidate, highly pipelined ASIC architectures with sophisticated internal data buffering which meet these constraints.