25 October 1988 VLSI Architecture For Generalized 2-D Convolution
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Proceedings Volume 1001, Visual Communications and Image Processing '88: Third in a Series; (1988) https://doi.org/10.1117/12.968985
Event: Visual Communications and Image Processing III, 1988, Cambridge, MA, United States
This paper proposes a VLSI architecture for the parallel processing of the generalized 2-D convolution. The processor consists of a shift-buffer pipeline, an array of multipliers and a tree of adders. The image data enter the processor in a raster scan format and are stroed and shifted in the pipeline. The multiplier array takes data from the pipeline and does the mulitiplication in parallel, and then sends the partial products to the adder tree to complete the computation. The simple architecture and control strategy makes the proposed scheme suitable for VLSI implementation.
© (1988) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yu-Chung Liao "VLSI Architecture For Generalized 2-D Convolution", Proc. SPIE 1001, Visual Communications and Image Processing '88: Third in a Series, (25 October 1988); doi: 10.1117/12.968985; https://doi.org/10.1117/12.968985

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