VLSI Architectures For Block Matching Algorithms

P. Pirsch; T. Komarek

doi:10.1117/12.969039

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25 October 1988 VLSI Architectures For Block Matching Algorithms

P. Pirsch, T. Komarek

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Proceedings Volume 1001, Visual Communications and Image Processing '88: Third in a Series; (1988) https://doi.org/10.1117/12.969039
Event: Visual Communications and Image Processing III, 1988, Cambridge, MA, United States

Abstract

This paper discusses architectures for realization of block matching algorithms with emphasis on highly concurrent systolic array processors. A three step mapping methodology for systolic arrays known from the literature is applied to block matching algorithms. Examples of 2-dimensional and 1-dimensional systolic arrays are presented. The needed array size, the transistor count and the maximum frame rate for processing video telephone and TV signals have been estimated.

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P. Pirsch and T. Komarek "VLSI Architectures For Block Matching Algorithms", Proc. SPIE 1001, Visual Communications and Image Processing '88: Third in a Series, (25 October 1988); https://doi.org/10.1117/12.969039

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