25 October 1988 VLSI Implementation Of Motion Compensation Full-Search Block-Matching Algorithm
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Proceedings Volume 1001, Visual Communications and Image Processing '88: Third in a Series; (1988); doi: 10.1117/12.969040
Event: Visual Communications and Image Processing III, 1988, Cambridge, MA, United States
Abstract
In this paper, we describe a single chip VLSI implementation of a Motion Compensation algorithm for a very low bit-rate motion video codec. Our design aims at implementing the Block Matching Algorithm (BMA). The novel features of our design are the followings: 1. It has full-search capability. 2. It allows sequential data inputs but performs parallel processing with 100% efficiency. 3. Common buses are used for data transfer. 4. It is a highly modular design and easy to expand. 5. It contains testing circuitry. The design has been laid out. Simulation results show that with the use of double metal 1.2µ CMOS process, the design will be able to run up to 25 MHz. The schematic design for fractional-precision block matching system is also described in this paper.
© (1988) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kun-Min Yang, Lance Wu, Hyonil Chong, Ming-Ting Sun, "VLSI Implementation Of Motion Compensation Full-Search Block-Matching Algorithm", Proc. SPIE 1001, Visual Communications and Image Processing '88: Third in a Series, (25 October 1988); doi: 10.1117/12.969040; https://doi.org/10.1117/12.969040
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KEYWORDS
Very large scale integration

Video

Parallel processing

Silicon

Astatine

Image processing

Metals

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