13 November 2016 FPGA-based real-time phase measuring profilometry algorithm design and implementation
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Phase measuring profilometry (PMP) has been widely used in many fields, like Computer Aided Verification (CAV), Flexible Manufacturing System (FMS) et al. High frame-rate (HFR) real-time vision-based feedback control will be a common demands in near future. However, the instruction time delay in the computer caused by numerous repetitive operations greatly limit the efficiency of data processing. FPGA has the advantages of pipeline architecture and parallel execution, and it fit for handling PMP algorithm. In this paper, we design a fully pipelined hardware architecture for PMP. The functions of hardware architecture includes rectification, phase calculation, phase shifting, and stereo matching. The experiment verified the performance of this method, and the factors that may influence the computation accuracy was analyzed.
© (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Guomin Zhan, Guomin Zhan, Hongwei Tang, Hongwei Tang, Kai Zhong, Kai Zhong, Zhongwei Li, Zhongwei Li, Yusheng Shi, Yusheng Shi, } "FPGA-based real-time phase measuring profilometry algorithm design and implementation", Proc. SPIE 10023, Optical Metrology and Inspection for Industrial Applications IV, 1002304 (13 November 2016); doi: 10.1117/12.2245375; https://doi.org/10.1117/12.2245375


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