28 September 2016 An FPGA-based reconfigurable DDC algorithm
Author Affiliations +
Proceedings Volume 10031, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016; 100314Y (2016) https://doi.org/10.1117/12.2249318
Event: Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016, 2016, Wilga, Poland
Abstract
This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.
© (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
B. Juszczyk, G. Kasprowicz, "An FPGA-based reconfigurable DDC algorithm", Proc. SPIE 10031, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016, 100314Y (28 September 2016); doi: 10.1117/12.2249318; https://doi.org/10.1117/12.2249318
PROCEEDINGS
6 PAGES


SHARE
Back to Top