The methodology used was the CMOS design cycle for integrated circuit design. All components of the pixel were designed from first principles to meet necessary requirements of a small pixel size (30×30 μm2) and an output resolution greater than that of an 8-bit ADC. For the photodetector, an n+-p+/p-substrate diode was designed with a parasitic capacitance of 3 fF. The analog front-end stage was designed around a Schmitt trigger circuit. The photo current is integrated on an integration capacitor of 200 fF, which is reset when the Schmitt trigger output voltage exceeds a preset threshold. The circuit schematic and layout were designed using Cadence Virtuoso and the process used was the AMS CMOS 350 nm process using a power supply of 5V.
The simulation results were confirmed to comply with specifications, and the layout passed all verification checks. The dynamic range achieved is 58.828 dB per pixel, with the output frequencies ranging from 12.341kHz to 10.783 MHz. It is also confirmed that the output frequency has a linear relationship to the photocurrent generated by the photodiode.