A general-purpose low-power two-stage CMOS amplifier circuit is designed and simulated for the ams 350 nm 5 V process. After the layout design and verification, the IC was submitted for a multi-project wafer manufacturing run. The simulated results are a bandwidth of 2.4 MHz, a common-mode rejection ratio of 70.04 dB, and power dissipation of 0.154 mW, which are comparable with the analytical values.
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P. Bezuidenhout, K. Land, T-H. Joubert, "A low-power CMOS operational amplifier IC for a heterogeneous paper-based potentiostat," Proc. SPIE 10036, Fourth Conference on Sensors, MEMS, and Electro-Optic Systems, 100360P (3 February 2017);