20 February 2017 CMOS-compatible optical AND, OR, and XOR gates using voltage-induced free-carrier dispersion and stimulated Raman scattering
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Proceedings Volume 10108, Silicon Photonics XII; 101080Q (2017) https://doi.org/10.1117/12.2251616
Event: SPIE OPTO, 2017, San Francisco, California, United States
Abstract
We present a theoretical model for two high-throughput optical logic methodologies, using voltage-induced free-carrier dispersion and stimulated Raman scattering based Zeno switching. Increased computational throughput is achieved by accessing higher switching speeds, optimizing the use of space, and by using multiple wavelengths for parallel processing. The condition of CMOS compatibility is maintained to take advantage of the high-volume, low-cost manufacturing potential of the industry and to help lower each design's spatial footprint (enabled by the high refractive index contrast of silicon-on-insulator waveguides and resonators). Each design is made with the potential of higher-order operations in mind; for their use must not only stand alone, but must also have the ability to incorporate into future all-optical or optoelectronic computational devices.
Conference Presentation
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Dusan Gostimirovic, Winnie N. Ye, "CMOS-compatible optical AND, OR, and XOR gates using voltage-induced free-carrier dispersion and stimulated Raman scattering", Proc. SPIE 10108, Silicon Photonics XII, 101080Q (20 February 2017); doi: 10.1117/12.2251616; https://doi.org/10.1117/12.2251616
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