23 February 2017 Improvement of sidewall roughness of sub-micron silicon-on-insulator waveguides for low-loss on-chip links
Author Affiliations +
Proceedings Volume 10108, Silicon Photonics XII; 1010816 (2017) https://doi.org/10.1117/12.2250344
Event: SPIE OPTO, 2017, San Francisco, California, United States
We report the successful fabrication of low-loss sub-micrometric Silicon-On-Insulator strip waveguides for on-chips links. Several strategies including post-lithography treatment, and post-Silicon smoothening techniques such as thermal oxidation and hydrogen annealing have been investigated to smoothen the waveguide sidewalls, as roughness is the major source of transmission losses. An extremely low silicon line edge roughness of 0.75nm is obtained with the optimized process flow combining resist mask Si patterning and hydrogen annealing at 850°C. As a result, record low optical losses of less than 0.5dB/cm are measured at 1310nm for waveguide dimensions superior to 500nm. They range from 2dB/cm to 0.8dB/cm for 300-400nm wide waveguides. Those results are to our knowledge the best ever published for a 1310nm wavelength.
Conference Presentation
© (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Cyril Bellegarde, Cyril Bellegarde, Erwine Pargon, Erwine Pargon, Corrado Sciancalepore, Corrado Sciancalepore, Camille Petit-Etienne, Camille Petit-Etienne, Vincent Hughes, Vincent Hughes, Jean-Michel Hartmann, Jean-Michel Hartmann, Philippe Lyan, Philippe Lyan, } "Improvement of sidewall roughness of sub-micron silicon-on-insulator waveguides for low-loss on-chip links", Proc. SPIE 10108, Silicon Photonics XII, 1010816 (23 February 2017); doi: 10.1117/12.2250344; https://doi.org/10.1117/12.2250344

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