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21 March 2017 Improved defectivity and particle control for nanoimprint lithography high-volume semiconductor manufacturing
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Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is cross-linked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate.

Criteria specific to any lithographic process for the semiconductor industry include overlay, throughput and defectivity. The purpose of this paper is to describe the technology advancements made in the reduction of particle adders in an imprint tool.

Hard particles on a wafer or mask create the possibility of creating a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, test stand results demonstrate the potential for extending mask life to better than 1000 wafers.
© (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Takahiro Nakayama, Masami Yonekawa, Yoichi Matsuoka, Hisanobu Azuma, Yukio Takabayashi, Ali Aghili, Makoto Mizuno, Jin Choi, and Chris E. Jones "Improved defectivity and particle control for nanoimprint lithography high-volume semiconductor manufacturing", Proc. SPIE 10144, Emerging Patterning Technologies, 1014407 (21 March 2017);

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