Process, design rule, and layout co-optimization for DSA based patterning of sub-10nm Finfet devices

Joydeep Mitra; Andres Torres; David Z. Pan

doi:10.1117/12.2257313

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21 March 2017 Process, design rule, and layout co-optimization for DSA based patterning of sub-10nm Finfet devices

Joydeep Mitra, Andres Torres, David Z. Pan

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Proceedings Volume 10144, Emerging Patterning Technologies; 101440G (2017) https://doi.org/10.1117/12.2257313
Event: SPIE Advanced Lithography, 2017, San Jose, California, United States

Abstract

Directed Self Assembly (DSA) has emerged as one of the most compelling next generation patterning techniques for sub-7nm via or contact layers. A key issue in enabling DSA as a mainstream patterning technique is the generation of grapho-epitaxy based guiding pattern (GP) shapes to assemble the contact patterns on target with high fidelity and resolution. Current GP generation is mostly empirical, and limited to a very small number of via configurations. In this paper, we propose the first model-based GP synthesis algorithm and methodology for on-target and robust DSA, on general via pattern configurations. The final post-RET printed GPs derived from our original synthesized GPs are resilient to process variations and continue to maintain the same DSA fidelity in terms of placement error and target shape.

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Joydeep Mitra, Andres Torres, and David Z. Pan "Process, design rule, and layout co-optimization for DSA based patterning of sub-10nm Finfet devices", Proc. SPIE 10144, Emerging Patterning Technologies, 101440G (21 March 2017); https://doi.org/10.1117/12.2257313

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