30 March 2017 Process resilient overlay target designs for advanced memory manufacture
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Abstract
In recent years, lithographic printability of overlay metrology targets for memory applications has emerged as a significant issue. Lithographic illumination conditions such as extreme dipole, required to achieve the tightest possible pitches in DRAM pose a significant process window challenge to the metrology target design. Furthermore, the design is also required to track scanner aberration induced pattern placement errors of the device structure. Previous workiii, has shown that the above requirements have driven a design optimization methodology which needs to be tailored for every lithographic and integration scheme, in particular self-aligned double and quadruple patterning methods. In this publication we will report on the results of a new target design technique and show some example target structures which, while achieving the requirements specified above, address a further critical design criterion – that of process resilience.
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Joonseuk Lee, Joonseuk Lee, Mirim Jung, Mirim Jung, Honggoo Lee, Honggoo Lee, Youngsik Kim, Youngsik Kim, Sangjun Han, Sangjun Han, Michael E. Adel, Michael E. Adel, Tal Itzkovich, Tal Itzkovich, Vladimir Levinski, Vladimir Levinski, Victoria Naipak, Victoria Naipak, Anna Golotsvan, Anna Golotsvan, Amnon Manassen, Amnon Manassen, Yuri Paskover, Yuri Paskover, Tom Leviant, Tom Leviant, Efi Megged, Efi Megged, Myungjun Lee, Myungjun Lee, Mark D. Smith, Mark D. Smith, Do-Hwa Lee, Do-Hwa Lee, DongSub Choi, DongSub Choi, Zephyr Liu, Zephyr Liu, } "Process resilient overlay target designs for advanced memory manufacture", Proc. SPIE 10145, Metrology, Inspection, and Process Control for Microlithography XXXI, 1014524 (30 March 2017); doi: 10.1117/12.2258376; https://doi.org/10.1117/12.2258376
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