28 March 2017 CD uniformity control for thick resist process
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Abstract
In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked flash cell array has been proposed. In constructing 3D NAND flash memories, the higher bit number per area is achieved by increasing the number of stacked layers. Thus the so-called “staircase” patterning to form electrical connection between memory cells and word lines has become one of the primarily critical processes in 3D memory manufacture. To provide controllable critical dimension (CD) with good uniformity involving thick photo-resist has also been of particular concern for staircase patterning. The CD uniformity control has been widely investigated with relatively thinner resist associated with resolution limit dimension but thick resist coupling with wider dimension. This study explores CD uniformity control associated with thick photo-resist processing. Several critical parameters including exposure focus, exposure dose, baking condition, pattern size and development recipe, were found to strongly correlate with the thick photo-resist profile accordingly affecting the CD uniformity control. To minimize the within-wafer CD variation, the slightly tapered resist profile is proposed through well tailoring the exposure focus and dose together with optimal development recipe. Great improvements on DCD (ADI CD) and ECD (AEI CD) uniformity as well as line edge roughness were achieved through the optimization of photo resist profile.
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Chi-hao Huang, Chi-hao Huang, Yu-Lin Liu, Yu-Lin Liu, Weihung Wang, Weihung Wang, Mars Yang, Mars Yang, Elvis Yang, Elvis Yang, T. H. Yang, T. H. Yang, K. C. Chen, K. C. Chen, } "CD uniformity control for thick resist process", Proc. SPIE 10145, Metrology, Inspection, and Process Control for Microlithography XXXI, 101452J (28 March 2017); doi: 10.1117/12.2256174; https://doi.org/10.1117/12.2256174
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