27 March 2017 CMOS patterning over high-aspect ratio topographies for N10/N7 using spin-on carbon hardmasks
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Abstract
In this paper proof-of-principle demonstrations of spin-on carbon (SOC)/spin-on glass (SOG)-based lithography processes which could replace standard patterning stacks within the FEOL for upcoming advanced nodes like N10/N7 are presented. At these dimensions the standard lithography approaches that have been utilized within the previous nodes will begin to run into fundamental limitations as a result of the extremely high aspect ratios of the device topography, requiring both new materials as well as new patterning flows in order to allow for continued device scaling. Here, novel SOC/SOG-based patterning flows have been demonstrated which could be applied to implement Source Drain Extension implantations and epitaxial growth processes for CMOS FinFET device architectures even down at N10/N7 dimensions.
Conference Presentation
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Toby Hopf, Toby Hopf, Monique Ercken, Monique Ercken, Geert Mannaert, Geert Mannaert, Eddy Kunnen, Eddy Kunnen, Zheng Tao, Zheng Tao, Nadia Vandenbroeck, Nadia Vandenbroeck, Farid Sebaai, Farid Sebaai, Yoshiaki Kikuchi, Yoshiaki Kikuchi, Hans Mertens, Hans Mertens, Stefan Kubicek, Stefan Kubicek, Steven Demuynck, Steven Demuynck, Naoto Horiguchi, Naoto Horiguchi, } "CMOS patterning over high-aspect ratio topographies for N10/N7 using spin-on carbon hardmasks", Proc. SPIE 10146, Advances in Patterning Materials and Processes XXXIV, 1014618 (27 March 2017); doi: 10.1117/12.2257668; https://doi.org/10.1117/12.2257668
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