27 March 2017 Optimize of shrink process with X-Y CD bias on hole pattern
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Gridded design rules[1] is major process in configuring logic circuit used 193-immersion lithography. In the scaling of grid patterning, we can make 10nm order line and space pattern by using multiple patterning techniques such as self-aligned multiple patterning (SAMP) and litho-etch- litho-etch (LELE)[2][3][4] . On the other hand, Line cut process has some error parameters such as pattern defect, placement error, roughness and X-Y CD bias with the decreasing scale. We tried to cure hole pattern roughness to use additional process such as Line smoothing[5] . Each smoothing process showed different effect. As the result, CDx shrink amount is smaller than CDy without one additional process. In this paper, we will report the pattern controllability comparison of EUV and 193-immersion. And we will discuss optimum method about CD bias on hole pattern.
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Kyohei Koike, Kyohei Koike, Arisa Hara, Arisa Hara, Sakurako Natori, Sakurako Natori, Shohei Yamauchi, Shohei Yamauchi, Masatoshi Yamato, Masatoshi Yamato, Kenichi Oyama, Kenichi Oyama, Hidetami Yaegashi, Hidetami Yaegashi, } "Optimize of shrink process with X-Y CD bias on hole pattern", Proc. SPIE 10146, Advances in Patterning Materials and Processes XXXIV, 101461N (27 March 2017); doi: 10.1117/12.2258221; https://doi.org/10.1117/12.2258221

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