This PDF file contains the front matter associated with SPIE Proceedings Volume 10147 including the Title Page, Copyright information, Table of Contents, Introduction, and Conference Committee listing.

As the industry marches on onto the 5nm node and beyond, scaling has slowed down, with all major IDMs & foundries predicting a 3-4 year cadence for scaling. A major reason for this slowdown is not the technical challenge of making features smaller, but effective control of variation that creeps in to the fabrication process. That variability manifests itself as edge placement error (EPE), which has a direct impact on wafer yield. Simply defined as the variance between design intent vs. actual on-wafer results, EPE is one of the foremost challenges being faced by the industry at the advanced node for both logic and memory. This is especially critical at three stages: the front end of line (FEOL) STI patterning; middle of line (MOL) contact patterning; and back end of line (BEOL) trench patterning where the desired tight pitch demands EPE control beyond the capability of 193i multi-patterning or even EUV single pattern. In order to mitigate this EPE challenge, we are proposing self-alignment of blocks & cuts through a multi-color materials integration concept. This approach, termed as “Self-aligned block or Cut (SAB or SACut)”, simply trades off the un-manageable overlay requirement into a more manageable etch selectivity challenge, by having multiple materials filled in every other trench or line.

In this paper we will introduce self-alignment based block and cut strategies using multi-color materials integration and show implementation for BEOL trench block patterning. We will present a breakdown of the key unit process challenges that were needed to be resolved for enabling the self-alignment such as: (a) material selection of multi-color approach; (b) planarization of spin on materials; (c) void-free gap fill for high aspect ratio features; and last but not the least, (c) etch selectivity of etching one material with respect to all other materials exposed. Further, we will present a comparison of our new self-alignment approach with standard approaches where we will articulate the advantages in terms of EPE relaxation and mask number reduction. We will conclude our talk with a brief snapshot of the future direction of our EPE improvement strategies and our view on the future of patterning beyond 5nm node for the industry.

Publisher’s Note: This paper, originally published on 30-March, 2017, was replaced with a corrected/revised version on 6-April, 2017. If you downloaded the original PDF but are unable to access the revision, please contact SPIE Digital Library Customer Service for assistance.

At advanced nodes, definition of design rules and process options must be tightly optimized to deliver the best tradeoff performance, power, area and manufacturability. However, implementation platforms don’t typically have access to process information and process teams don’t have design knowledge, and optimization loops required for Design-Technology-Co-Optimization (DTCO) are either impossible or at best long and expensive for fabless design house.

Joining forces, ASML, IMEC and Cadence Design Systems developed an In-design and signoff lithography physical analysis well suited for 7/5nm and below. The Tachyon OPC+ engine used by IMEC 7/5nm process has been integrated in Cadence Litho Physical Analyzer (LPA) to perform lithography checks using the foundry process models, recipes, and hotspot detectors. This flow leverages existing LPA infrastructure for both custom and digital design platforms, as well as standalone signoff.

Depending upon the end application, LPA could be launched either from place & route or custom layout or standalone. LPA processes first the design database to identify hierarchy, decompose the layout for coloring and apply pattern matching to identify location requiring simulation. The layout is then passed to the Tachyon OPC tool to perform optical process correction and model-based litho verification that is validated on Silicon. The hotspots and contours are processed by LPA for generation of hotspot marker and fixing guidelines and provide all this information to the design environment.

The flow has been developed and demonstrated to work on IMEC 7nm, and can be ported to smaller or larger technologies. The paper will present the result of this In-design and signoff lithography physical analysis flow, how DTCO and design teams can add manufacturability to PPA.

A heuristic optimization approach has been developed to optimize SRAF (sub resolution assist feature) placement rules for advanced technology nodes by using a genetic algorithm. This approach has demonstrated the capability to optimize a rule-based SRAF (RBSRAF) solution for both 1D and 2D designs to improve PVBand and avoid SRAF printing. Compared with the MBSRAF based POR (process of record) solution, the optimized RBSRAF can produce a comparable PVBand distribution for a full chip test case containing both random SRAM and logic designs with a significant 65% SRAF generation time reduction and 55% total OPC time reduction.

Over the years, lithography engineers continue to focus on CD control, overlay and process capability to meet current node requirements for yield and device performance. Use of ArFi lithography for advanced process nodes demands challenging patterning budget improvements in the range of 1/10 nm especially for interconnect layers.⁽¹⁾ Previous experimental and simulation based investigations into the effects of light source bandwidth on imaging performance have provided the foundation for this work.^(2-6) The goal from the light source manufacturer is to further enable capability and reduce variation through a number of parameters.(^7-10)

In this study, the authors focus on the increase in image contrast that Source Mask Optimization (SMO) and Optical Proximity Correction (OPC) models deliver when comparing 300 fm and 200 fm light source E95% bandwidth. Using test constructs that follow current N7 / N5 ground rules and multiple pattern deconstruction rules, improvements in exposure latitude (EL), critical dimension (CD) and mask error enhancement factor (MEEF) performance are observed when SMO and OPC are optimized for 200 fm light source bandwidth when compared with the standard 300 fm bandwidth. New SMO-OPC flows will be proposed that users can follow to maximize process benefit. The predicted responses will be compared with the experimental on wafer responses of 7 nm features to lower light source bandwidth.

This talk will describe computational imaging methods for phase retrieval of mask effects, such as electromagnetic edge effects. Our experimental setups employ illumination-side or detection-side coding of angle (Fourier) space with simple hardware. The result is high-resolution intensity and phase images for quantifying mask edge effects. We describe methods for illumination coding Gigapixel microscopy in commercial microscopes and extend our methods to 3D imaging and algorithmic self-calibration. Through an end-to-end design of both the optical system and the computational algorithms, we achieve metrology modalities that are accurate, simple and flexible.

The next generation technology and emerging memory devices require gradually tighter lithographic focus control on imaging critical layers. Especially in case of BEOL process, big PDO (Process Dependent Offset) from large intra-field topography steps affects the process margin directly. There are couple of scanner options to reduce PDO, such as AGILE which provides several benefits. However, for certain use cases the AGILE sensor may not be the optimal solution.

In this paper, we introduce the concept and development background of iFPC (intra-field Finger Print Correction). iFPC is a scanner option that removes the generic 3D fingerprint seen in the leveling data so that both process dependency and actual wafer topography are not followed during wafer exposure.

In addition, we compare the degree of process margin improvement when applying iFPC compared to that of AGILE on a critical layer. The achieved results demonstrate that by applying iFPC it is possible to gain an additional 15~20nm DoF. In other words, on this use case our feasibility suggests that by removing the generic 3D fingerprint seen in the leveling data, it is possible to achieve a better focus performance than when trying to follow the topography during scanning.

In conclusion, we found another good way to improve the process margin through this comparative experiment. Therefore, our next step will be to setup the methodology to select the use cases where iFPC is the optimal solution.

Shrinking pattern sizes dictate that scanner-to-scanner variations for HVM products shrink proportionally. This paper shows the ability to identify (a subset of) root causes for mismatch between ArF immersion scanners using scanner metrology. The root cause identification was done in a Samsung HVM factory using a methodology (Proximity Matching Budget Breakdown or PromaBB) developed by ASML. The proper identification of root causes^-1 helps to select what combination of scanner control parameters should be used to reduce proximity differences of critical patterns while minimizing undesirable side effects from cross-compensation. Using PromaBB, the difference between predicted and measured CD mismatch was below 0.2nm. PromaBB has been proposed for HVM implementation at Samsung in combination with other ASML fab applications: Pattern Matcher Full Chip (PMFC), Image Tuner and FlexWave.

With each technology node, overall focus budgets have become increasingly tighter in order to meet the necessary product requirements. The 7nm node has required us to define new opportunities for addressing top contributors to the focus budget. Field curvature in particular has been identified as a key contributor to the intrafield focus budget, contributing around 50%. This paper will introduce two new methodologies for improving field curvature; one a hardware solution and one a software solution.

The Global 450mm Consortium (G450C), which is located at the SUNY Poly campus in Albany, NY was created to develop and evaluate a manufacturing tool set for 450mm wafers. The Lithography cell at G450C consists of a Nikon NSR-S650D 193nm immersion scanner and a SCREEN SOKUDO DUO DT-4000 track. The Lithography cell was installed and qualified in 2015, and with over a year of tool availability we have been able to perform extensive testing on the system to determine the equipment readiness for volume manufacturing. For the purposes of this paper we are focusing on the Edge Placement Error (EPE) [1] contributors of Critical Dimension Uniformity (CDU) and Overlay [2]. We will show the initial results as well as the improvements that have been made since tool acceptance. The 450mm results will be compared to 300mm tools in production today, as well as against the seven nanometer node (N7) expected requirements. Lastly, we plan to demonstrate the Nikon scanner’s ability for focus control on stressed or bowed wafers, which are characteristic challenges of large silicon substrates. This paper will showcase the current 450mm lithography performance for CDU on both Line/Space (LS) and Contact Hole (CH) patterns. We will demonstrate the process window for LS and CH features on multiple resists specially formulated for 450mm. Both Post Exposure Bake (PEB) tuning on the SCREEN track as well as CDU Master (CDUM) Corrections from the Nikon Turnkey Solution software suite will be utilized for performance improvements on 450mm wafers. The G450C goal is to drive CDU down to less than 1nm 3σ across the entire wafer with 1.5mm edge exclusion zone.” In addition to our test masks, G450C has designed a three layer mask set and with these masks we gathered “on product” CDU performance on a Back End Of Line (BEOL) metal stack. In the current reality of high volume manufacturing, multi-patterning is used to achieve the required Critical Dimension (CD) and pitch combination. The largest contributor to EPE is scanner overlay performance. We will demonstrate the Single Machine Overlay (SMO) performance as well as some Mix and Match Overlay (MMO) results. The lithography cell at G450C is the only 450mm linked lithography cell in the world. In order to create MMO wafers we were required to expose the first print at the Nikon factory in Japan and etch them at G450C to generate an align-to layer. As the wafers’ size scales, so do some of the process effects including film stress and wafer bow. The current G450C BEOL integrated process has measured wafer bow of up to 350um. We will demonstrate how the S650D measures the wafer topography and adjusts the exposure to compensate for wafer bow.

Fifteen years has passed since ArF lithography technology transitioned to mass production. At first the node size was 130nm, however, now we are discussing one-digit nm node. This node size is one-fifteenth compared to that in the initial generation. It is obvious that generations have steadily changed. Meanwhile, ArF projection optics has been designed with higher NA. Moreover, much higher NA or effectively short wavelength have been achieved by introducing the immersion lithography technology which injects immersion media between the light emission side of optics and the wafer surface. Now that ten years has passed since the immersion lithography technology transitioned to mass production, the requirements for the light source have become much more demanding. This is because E95%, a typical parameter for the light source, which reduces the CD variation and influences the optical characteristics, has been required to be much shorter along with advanced node. The spectrum characteristics of the conventional KrF 248nm-light source were defined with full-width at half maximum (FWHM). After entering ArF era, E95% was defined as more stringent parameter. This new parameter is closely linked to line narrowing and node transition. This E95% is a parameter to define optics monochromaticity and recognized as equivalent to quantified chromatic aberration. More specifically, it is desired to reduce the chromatic aberration ideally down to zero to maximize the contrast by suppressing blur images. Provided that the blur images are caused by not only chromatic aberration but also the convoluted effect of spherical aberration, residual errors of lithography optics system and other defocus elements. In line with this we should take persistent challenges to reduce errors in designing and manufacturing lithography optics systems and drive the chromatic aberration closer to zero. The contrast we discuss in the lithography optics systems strongly correlate to resolution, and thus it is well known that OPC bias is linear with respect to E95% when the resolution is fixed. Although this OPC bias and E95% have been firmly linear with each other, it has also been revealed that the trend of the linearity with much shorter E95% deviates from the conventional trend and shows an inflection point in the near future. We systematically analyze the trend that linearity error tends to be greater than the conventional distribution and suggest solutions to the issue. This systematic analysis includes: 1. Measurement errors and distribution in measuring E95% as the spectrum width 2. Correlation between raw measured spectrum intensity data and E95% 3. Linearity comparison in behaviors between when E95% is approximated by i) +/-2 sigma of, ii)+/-3 sigma of normal spectrum distribution, and iii) by another approximation. Based on these studies, we identify the roles of the light source to contribute to 7nm-node mass production by defining the spectrum and its requirements for lithography performance.

Figure would be provided Figure 1 shows that the most important factor in lithography is foot contrast. Low contrast leaves a large region (CAT) where resist solubility is uncertain (chaotic area), which causes unresolvable patterns, LER/LWR issues, and pattern collapse (collapse may be due to affinity imbalance). Figure 2 shows examples of a CAT plot for two stacks of low optical reflectivity and high optical foot contrast. Low reflectivity gives higher CAT, and is further deteriorated as the image approaches the forbidden pitch, while a high foot contrast stack keeps good CAT value across all pitches. Experimental results agree well with the calculations, which will be included in the full paper. Figure 3 is a CAT contour map versus resist and Si-HM thickness for a L/P=40/100 nm pattern. Additional CAT plots will be included in the full paper. Figure 1. Optical distribution of a 40-nm dense line cross-section and resist contrast curve for CAT calculation. Figure 2. CAT plots comparing two stacks, low reflectivity and high foot contrast Figure 3. CAT contour map versus resist and Si-HM thickness.

Simulation of negative tone development (NTD) resist has become a challenge for physical resist modeling. Traditionally, resist modeling was mainly limited to reaction-diffusion models for post exposure bake (PEB) and standard development rate models for simulating the pattern formation during the final development step. With some minor extensions, this simulation approach sufficiently predicted resist CDs and resist profile shapes that were in agreement with experimental data.³ For the latest NTD resists, this situation has changed. In contrast to positive tone development (PTD) resists, resist shrinkage is strongly impacting resist profile shapes. Furthermore, NTD resists induce strong proximity effects that require consideration of additional chemical resist properties in modeling and model calibration. In this paper we experimentally characterize and model the main properties of NTD photo-resists.

The effects of photoresist sidewall profile and LER on two representative integration schemes were studied through 3D virtual fabrication: Front-End of Line (FEOL) Fin formation and Back-End of Line (BEOL) Metal line definition. Both of these processes use self-aligned double patterning (SADP) in pattern definition, and affect the circuit performance through MOSFET channel shape and parasitic capacitance respectively. In both cases we imposed LER and sidewall roughness on the photoresist that defines the mandrel at the initial step of the SADP flow using SEMulator3D. The LER followed a Gaussian correlation function for a number of amplitude and correlation length values. The sidewall profile emulated the bulb-shaped pattern that is reported in experimental works. The taper angle and roughness amplitude of this shape were varied to isolate its components. In each of these cases, we have found direct evidence of resist sidewall profile impact on variability degradation in CD and electrical performance. Special care should be placed on controlling resist profile through optimization of exposure and development schemes.

With shrinking design rules, the overall patterning requirements are getting aggressively tighter and tighter. For the 5-nm node and beyond, on-product overlay below 2.5nm is required. Achieving such performance levels will not only need optimization of scanner performance but a holistic tuning of all process steps. In previous work, it has been shown that process-induced pattern asymmetry has significant impact on overlay performance at wafer edge and can be partially compensated by applying high-order scanner corrections or optimizing metrology targets. Today, we present the reduction of process-induced pattern asymmetry in a tunable etch system and demonstrate the related on-product overlay improvement combined with scanner corrections.

In our work we utilize etch tools (Lam Kiyo® conductor etch systems) with proprietary edge tuning technology that can be used to reduce the etch-related asymmetry at the wafer edge. In combination to this unique method, we evaluate the impact of high order corrections per exposure field to compensate for process asymmetry at the wafer edge with a state-of-the-art 1.35 NA immersion scanner (NXT:1970Ci).

The study is done on dedicated test wafers with 10-nm logic node design. We use angle-resolved scatterometry (YieldStar® S-250), atomic force microscopy, and SEM cross-sections to characterize process asymmetry. We present experimental investigation of the effect of etch tuning and scanner corrections on the pattern shift and the resulting overlay. In particular, we present results showing a reduction of etch-induced pattern shift by 12nm at wafer radius 147mm.

Results show that asymmetry can be addressed by both, litho compensation and etch tuning, and bring on-product overlay down to the required level. We discuss the benefit of the correction techniques especially for thick hard mask layers (the pattern shift scales linear with hard mask thickness) and evaluate a combined correction scenario, where preventive etch tuning and feed-back based scanner corrections are used. We conclude that a holistic tuning of all process steps will be required to fulfill overlay requirements of future nodes.

Successful patterning requires good control of the photolithography and etch processes. While compact litho models, mainly based on rigorous physics, can predict very well the contours printed in photoresist, pure empirical etch models are less accurate and more unstable. Compact etch models are based on geometrical kernels to compute the litho-etch biases that measure the distance between litho and etch contours. The definition of the kernels as well as the choice of calibration patterns is critical to get a robust etch model. This work proposes to define a set of independent and anisotropic etch kernels designed to capture the finest details of the resist contours and represent precisely any etch bias. By evaluating the etch kernels on various structures it is possible to map their etch signatures in a multi-dimensional space and analyze them to find an optimal sampling of structures to train an etch model. The method was specifically applied to a contact layer containing many different geometries and was used to successfully select appropriate calibration structures. The proposed kernels evaluated on these structures were combined to train an etch model significantly better than the standard one.

Various multi-patterning processes with associated design methodologies have been deployed to address patterning challenges of ArFi and alternate solutions such as EUV, DSA or nanoimprint. Process variability prediction through compact models is sometimes limited to those multipatterning processes used to compose single final target. We may call those sequential processes as representative module for design target layer which is not clearly derived from single litho-etch process but derived from the interaction between various layers. Key challenges for extending multiple pattering are managing design and tolerance variation in multiple pattering steps with proper restrictions, and visualizing interlayer errors (w/ bridge & pinch and overlap). Additionally,visualization of final target layers and intermediate layers is important for process/design engineers.

We will demonstrate verification flows for different process modules to verify the failure mechanisms and to aid in visualization, then judge the areas for improvement with existing model based solutions. Then we will also try to investigate possible area for development of accurate residual error prediction from compact models as those errors are accumulated from multiple process effects into final CD measurement from design target layers. This may lead to new dimensions of modeling process effects we’ve never considered because those signatures were lumped between processes to processes.

Lithography simulation is an essential technique for today's semiconductor manufacturing process. In order to calculate an entire chip in realistic time, compact resist model is commonly used. The model is established for faster calculation. To have accurate compact resist model, it is necessary to fix a complicated non-linear model function. However, it is difficult to decide an appropriate function manually because there are many options. This paper proposes a new compact resist model using CNN (Convolutional Neural Networks) which is one of deep learning techniques. CNN model makes it possible to determine an appropriate model function and achieve accurate simulation. Experimental results show CNN model can reduce CD prediction errors by 70% compared with the conventional model.

In this paper we introduce an inverse lithography technology (ILT) solution that provides masks with perfect symmetry and minimal complexity. In this solution we divide the ILT problem into three steps and strictly maintain symmetry in each of these steps. First, we optimize an ideal grayscale mask. Second, we seed this ideal mask with polygons. Finally, we grow these seeds in a separate optimization flow. The final mask perfectly maintains the symmetry properties of the illumination source. To the best of our knowledge, this is the first ILT solution that can be used on the original design hierarchy on a full chip scale.

Most pattern shift analysis discussions focus on the accuracy of the Optical Proximity Correction (OPC) model that forms the pattern contours, while the OPC model’s source itself is considered as a constant input to the model. In reality, the source might have defects or contaminations that can impact the image formation and possibly introduce asymmetrical pattern formation behavior. Initial studies have quantified the impact of source defects on wafer CDs in the presence of OPC [1]. These studies have found that when source defects are present in the OPC model CD variation, NILS impact, MEEF impact, and pattern shifts might occur. Empirical studies and data have shown that the severity of defects are proportional to the impact on final pattern formation. However, it should also be noted that optical proximity correction schemes have been found to be a robust ally in countering the aforementioned defects in imaging.

This study is a continuation of the previous work of source imperfection impacts on optical proximity correction to better understand the interaction between source defects and pattern shift during mask synthesis. Two variations of the study are executed: the first variation is the mask error case where random intensity variations are introduced in the pixelated source and an OPC model is created, then the corrected pattern is imaged with an ideal source. The second variation is the exposure error case where the OPC correction is performed with an ideal source, then exposed with a random defect in the manufacturing source. For both cases a pixel transmission variation is introduced in pixelated source using 11 various pixel selection methodology. Each experiment for the mask and exposure defects are conducted five times. This aims to quantify the effects on pattern uniformity while assuming defects in source manufacturing. This also allows you to better understand the limitation of scanner systems that might not be able to 100% represent the source pixels that were created during an aggressive Source Mask Optimization (SMO) session. Detailed analysis and studies are conducted to quantify the source defects impact on pattern formation.

DUV immersion lithography (ArFi) continues to be the primary lithographic method for semiconductor manufacturers. Use of ArFi lithography requires patterning budget improvements in the range of 1/10 nm especially for interconnect layers^[1] ; for advanced process technology nodes, every Angstrom counts. Previous investigations into the effects of light source bandwidth on imaging performance have provided the foundation for this work^[2-10]. This study will focus on the increase in image contrast that 200 fm light source E95 bandwidth enables on Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) features. The impact of 200 fm E95 bandwidth on the CD and Edge Placement Error (EPE) performance of core (grating) and block features will be assessed using an imec 7 nm process node test vehicle. The on wafer experimental results will be compared with the simulation predicted responses of the target features to lower light source bandwidth.

Sub-Resolution Assist Feature (SRAF) printing is a critical yield detractor and known issue in OPC technology. SRAF print avoidance models can be used to determine where undesirable printing is likely to occur, but such models lack the necessary robustness and reliability for the detection of all SRAF printing cases. Classification of printing SRAFs is a subjective and manual task where many engineering hours are spent. In this work we demonstrate a reliable way to accurately classify images according to SRAF printing risk. Testing multiple sets of data, across multiple processes, yielded a prediction success rate of 97% wherein only a single image was under-predicted. Under-prediction is when a model fails to predict printing SRAFs; a key defect generator, as it means the model will not be able to remove the SRAF shape in the OPC iteration before mask build. We propose a new methodology as to accurately auto-classify and filter images with SRAF printing on wafer. This scalable solution will improve the quality and reliability of SRAF print avoidance models and reduce the risk of printing SRAF by removing the manual, highly subjective, image classification step.

A new form of image decomposition is derived that uses compound systems to target critical TCC components while at the same time providing the usual least-squares optimal match to the TCC as a whole. Significant improvements in accuracy under a given runtime budget are obtained by intensively correcting those portions of the TCC which are most recalcitrant to the standard coherent decomposition used in OPC today (e.g. SOCS or OCS). In particular, the non-coherent structure of our new decomposition systems is well-suited to extract any near-Toeplitz components present in the spatial-domain TCC. Such components are difficult to capture with coherent decomposition, and we show that TCCs for lithographic systems in fact contain strong Toeplitz-like components that arise from slope discontinuities associated with the sharp aperture of the projection lens. 1D tests show that for a given kernel-count budget in the typical e.g. 10-100 range, image calculation error can routinely be reduced by at least 5X if our new systems are included in the decomposition.

New inverse methods such as model-based SRAF placement, model-based SRAF optimization, and full main + assist feature ILT are well known to have considerable benefits in finding flexible mask pattern solutions to improve process window and CD control. These methods have traditionally relied on compact models that are tuned to match resist measurements at a single z-height or slice. At this slice in the resist, some critical failure modes such as top loss and scumming are not detected. In this paper, we describe and present results for a methodology to extend ILT’s process window improvement capabilities, and to co-optimize mask patterns with awareness of the resist profile. These improvements are proven to reduce the risk of patterning failures at the bottom and top of critical resist features, which a typical mask correction process would not alleviate. Ideally, mask optimization would use a full rigorous TCAD resist model to guide the correction at multiple heights in the resist. However, TCAD models are significantly slower than compact models in simulations and ILT already has high computational requirements. Therefore, we have generated compact models which are fitted to the TCAD model resist profile data. We show the significant process window improvements obtained with this new resist 3D aware ILT methodology.

State-of-the-art OPC recipes for production semiconductor manufacturing are fine-tuned, often artfully crafted parameter sets are designed to achieve design fidelity and maximum process window across the enormous variety of patterns in a given design level. In the typical technology lifecycle, the process for creating a recipe is iterative. In the initial stages, very little to no “real” design content is available for testing. Therefore, an engineer may start with the recipe from a previous node; adjust it based on known ground rules and a few test patterns and/or scaled designs, and then refine it based on hardware results. As the technology matures, more design content becomes available to refine the recipe, but it becomes more difficult to make major changes without significantly impacting the overall technology scope and schedule. The dearth of early design information is a major risk factor: unforeseen patterning difficulties (e.g. due to holes in design rules) are costly when caught late.

To mitigate this risk, we propose an automated flow that is capable of producing large-scale realistic design content, and then optimizing the OPC recipe parameters to maximize the process window for this layout. The flow was tested with a triple-patterned 10nm node 1X metal level. First, design-rule clean layouts were produced with a tool called Layout Schema Generator (LSG). Next, the OPC recipe was optimized on these layouts, with a resulting reduction in the number of hotspots. For experimental validation, the layouts were placed on a test mask, and the predicted hotspots were compared with hardware data.

We demonstrate a fundamental paradigm shift in microoptics manufacturing. Using femtosecond two-photon 3D printing with 100 nm spatial resolution, the time from lens design and structural assembly layout to manufacturing and optical testing can be reduced to less than 24 hours. Even complex microscope objectives with multiple aspherical and non rotationally symmetric freeform surfaces can be manufactured. We demonstrate diffraction limited performance and MTF measurements across a large field of view of such systems that can be as small as only 100 µm in diameter, directly fabricated onto the ends of optical fiber tips. Other applications such as phase shapers or miniaturized illumination systems are also presented.

Laser Direct Write Lithography (LDWL) is a serial maskless lithography technique where a focused laser beam is scanned through a photoresist. We present a simulation flow for LDWL that includes focusing of Gaussian beams, free radical polymerization chemistry of the resist, and photoresist development. The developed simulation flow was applied to analyze the results of an experiment where laser direct write lithography is combined with Nanoimprint lithography. Specifically, we investigate the root causes of experimental observations on the improvement of the process performance by sub-division of the total exposure dose into several discrete writing cycles, which are separated in time. In addition, the developed modeling approach is used to investigate innovative laser write methods: two photon absorption (TPA), stimulated emission depletion (STED) lithography, and quencher diffusion assisted lithography.

We analyzed the field contrast, aspect ratio, pattern uniformity as well as the line-edge roughness (LER) of the patterns fabricated in plasmonic lithography. Deep subwavelength patterns with high aspect-ratio and large-area uniformity were achieved by coupling the evanescent waves into an optical waveguide as well as the selection of a single high spatial frequency mode. In addition, the impacts of defects on photomasks and the surface roughness on thin films are studied in two exemplary plasmonic lithography systems: superlens and hyperbolic metamaterials (HMM). Superlens is capable of replicating arbitrary patterns, which also inherently make it vulnerable to roughness of the thin film and imperfections on the mask; while HMM system is more immune to such imperfections due to its spatial frequency selection function property.

Plasmonics based photolithography has been able to achieve pattern size beyond the typical diffraction limit by exploiting the surface plasmon (SP) [1]. However, film roughness is inevitable in practical fabrication, and can strongly impact the performance of the lithography. In our work, exemplary lithography systems including superlens and hyperbolic metamaterial (HMM) based approaches are considered, where the effects of films roughness and the defects on the mask are analyzed systematically. For the superlens system, a chromium (Cr) mask with thickness of 50 nm and period of 90 nm on glass substrate, is placed above the superlens with a poly-methyl-methacrylate (PMMA) spacer layer. A silver (Ag) film with thickness of 20 nm transmits the transverse magnetic (TM) polarized light with wavelength 365 nm the photoresist (PR) film with thickness of 40 nm. A reflector composed of an Ag film with thickness of 50 nm is added at the bottom of the PR. For the HMM system, Cr mask is used with period of 360 nm and the multi-layer structure is composed with 9 layers of 15 nm thick aluminum (Al) and 30 nm thick silicon dioxide (SiO2) films. The PR is also 40 nm and reflector film is an Al film with thickness of 50 nm. The broad optical transfer function (OTF) of the smooth Ag enables the evanescent waves of wide wave vector range to pass through [2]. While the OTF of HMM shows that only ±2nd order diffraction waves with the wave vector about 2k_0 can pass through [3]. Different degrees of roughness are introduced on the films and the photomask, and the performance of the two systems in terms of the intensity, pattern uniformity and line edge roughness are compared. As the roughness of the films grows, the OTF of the superlens degrades dramatically, while the OTF of the HMM maintains, as shown Figure 1 and 2. Accordingly, the field distribution of the HMM system is less affected by the film roughness, thereby can still produce high quality periodic patterns. By properly choosing the period of the mask, the desired transmission order coincides with the peak of the OTF function. Therefore, the light of desired spatial frequency transmits maximally, while the other diffraction orders induced by the rough surfaces is relatively suppressed, leading to a pattern with better uniformity. On the other hand, the superlens case does not offer such a utility because of the broad transmission function in OTF. But superlens can image arbitrary patterns; while the drawback is that line-edge roughness of the mask will also be imaged onto the photoresist. Therefore, the impact of a single defect on the mask pattern is much greater than that of the HMM approach. In addition, the waveguide lithography system consists of aluminum (Al) layers acting as a filter shows similar behavior compared with that of the HMM system. Though the structure is almost identical to the superlens structure, but the thin metal film serves a very different function in this case, which confirms the distinctive advantage of the frequency selective scheme. Meanwhile, our simulation shows Al can be a good superlens at 193 nm, which indicates that the same metal can function differently in different schemes or wavelengths.

We investigated the fabrication of small neuroelectronic device consisting of four shanks with 16 electrodes per shank for simultaneous neurochemical and brain activity monitoring. The 16 electrodes on each shank have a separation distance of 100 microns (μm). Each shank has a width of 40 μm with separation distance of 7750 μm. This design eliminates single-site recording with limited individual conductors and permits rapid characterization of multiple neurons simultaneously at multiple brain depth/sites, consequently providing ground-breaking capabilities for parsing neurochemical release and brain activity. The device is fabricated on (100) silicon substrate and is fully integrated with electrode, interconnect and bond pad fabricated on one chip. Gold rectangular pyramid electrodes are selected as the recording electrodes to enhance the non-invasiveness associated with heating and minimizing surrounding biological tissue damage. The gold electrodes are deposited on the etched silicon substrate with 600 nanometer (nm) low temperature oxide (LTO) sacrificial layer. Each electrode has top area of 6 μm x 60 μm and depth of 750 μm. The interconnects provide electrical connection between electrodes and bond pads and are sandwiched between thin polyimide layers to prevent them from breaking while maintaining the flexibility. Final bond pads and electrodes are all passivated with polyimide to provide mechanical support. Upon device release, the recording electrodes are exposed to directly contact brain structure, and the exposed bond pads are soldered on the circuit board to transport signals to the measurement instrument. The entire process involves five photomasks. Process development and integration challenges will be reviewed and discussed in the paper.

Previous studies have quantified the impact of source error on wafer CDs in the presence of OPC. The studies found that when a 100% emitting source error is introduced into the OPC model, the corrected mask is minimally impacted through process when small errors are introduced on the source. However, as slightly larger errors are placed on the source used in the OPC mode, catastrophic failures are found. When the same errors are introduced to the exposure source when the mask is corrected with a perfect source, there is a significant through process CD variation in the system but there are no clearly catastrophic failures.

The present study continues beyond the initial work to better understand the interaction between source errors and OPC. In this case, partial transmission and zero transmission errors are introduced into the study. The initial study found a CD bias and extra CD variation when the error was located in the transmissive area for the source error case. As the result of a previous study, these effects are thought to be due to scattered background illumination and pattern shift, respectively. These effects were not as readily observed in the mask error case. This study looks at the interaction of different errors in the source during both exposure and OPC generation to better understand the effects of source errors on the final pattern.

A resulting analysis of study is presented. The analysis explains whether scattered background illumination and pattern shift are the mechanisms of the source effects. This can be concluded if the same effects can be generated in the mask error case using various source errors. The software methodology used to execute these studies is presented in detail.

The appropriate representation of the photomask in the simulation of wafer lithography processes has been shown to be of vital importance for 14-nm and below [1]. This task is difficult, since accurate optical metrology and physical metrology of the three-dimensional mask structure is not always available. OPC models for wafer patterning comprise representations of the mask, the optics, and the photoresist process. The traditional calibration of these models has involved empirical tuning of model parameters to CD-SEM data from printed photoresist patterns. Such a flow necessarily convolves the resist effects and it has been difficult to reliably obtain mask and optical parameters which are most representative of physical reality due to aliasing effects. In this work, we have undertaken to decouple the mask model from the photoresist process by use of the ZEISS Wafer-Level CD (WLCD) tool based upon aerial image metrology. By measuring the OPC test pattern mask with WLCD, the mask parameters in the OPC model can be tuned directly without interference of resist effects. This work utilized 14-nm,10-nm, and 7-nm node masks, and we demonstrate that the use of such a flow leads to the most predictive overall OPC models, and that the mask parameters resulting from this flow more closely match the expected physical values. More specifically, the mask corner rounding, sidewall angle, and bias values were tuned to the WLCD data instead of the wafer CD SEM data, and resulted in improved predictive capability of the model. Furthermore, other mask variables not traditionally tuned can be verified or tuned by matching simulation to aerial image metrology.

The extension of optical lithography to 7 nm node and beyond relies heavily on multiple litho-etch patterning technologies. The etch processes in multiple patterning often require progressively large bias differences between litho and etch as the target features become smaller. Moreover, since this litho-etch bias has strong pattern dependency, it must be taken into consideration during the Optical Proximity Correction (OPC) processes. Traditionally, two approaches are used to compensate etch biases: rule-based retargeting and model-based retargeting. The rule-based approach has a turn-around-time advantage but now has challenges meeting the increasingly tighter critical dimension (CD) requirements using a reasonable etch-bias table, especially for complex 2D patterns. Alternatively, model-based retargeting can meet these CD requirements by capturing the etch process physics with high accuracy, including the etch bias variability that arises from both patterning proximity effects and etch chamber non-uniformity. In the past, empirical terms have been used to approximate the etch bias due to pattern proximity effects but sometimes empirical models are known to have compromised model accuracy so a physical based approach is desired. This paper’s work will address the etch bias variability due to patterning proximity effects by using a physical approach based simplified chemical kinetics. It starts from a well calibrated After-Development-Inspection (ADI) model and the subsequent etch model is based on the ADI model contour. By assuming that plasma chemical species in the trenches are maintained in an equilibrium state, the plasma species act on the edges to induce etch bias. Methods are developed to evaluate plasma collision probability on trench edges for random layouts. Furthermore, the impact of resist materials on etch bias are treated with Arrhenius equation or as a second order reaction. Equations governing plasma collision probabilities on trench edges as a function of time are derived. An etch bias model can be calibrated based on those equations. Experimental results have shown that this physical approach to model etch bias is a promising direction to applications for full-chip etch proximity corrections.

The layout design for silicon photonics can be complicated and usually have edges with arbitrary angles. The critical dimension can be less than 100 nm, requiring the layouts to be OPCed in order to have large enough process windows for high volume manufacturing. However, the well-established CMOS-orientated IC industry OPC tools for advanced nodes can only handle Manhattan designs in which the Manhattan style polygons with edges of 0°, 90° or 45° to the reference direction. Silicon photonics layouts need to be discretized in order to use the existing OPC tools. From optical performance point of view, the design grid is expected to be as small as possible and it is usually from 1 nm to 5 nm. However, the design grid has never been optimized based on the OPC performance. In this paper, we demonstrate the impacts of design grid on the OPC performance. Design grid for silicon photonics is not always the smaller the better anymore. Our study shows that small 2D designs require large design grids while smooth curves with large radius require small design grids. We proposed a novel design-based discretization algorithm to convert a non-Manhattan style layout to an OPC-friendly Manhattan style layout. Simulation results show that the pattern fidelity is optimized for both small 2D patterns and smooth curves.

Si-Photonics is the technology in which data is transferred by photons (i. e. light). On a Photonic Integrated Circuit (PIC), light is processed and routed on a chip by means of optical waveguides. The Si-Photonics waveguides functionality is determined by its geometrical design which is commonly curved, skew and non-Manhattan. That is why printing fidelity is very challenging on photonics patterns.
In this paper, we present two different Optical Proximity Correction (OPC) flows for Si-Photonics patterning. The first flow is regular model based OPC and the second one is based on Inverse Lithography Technology (ILT). The first OPC flow needs first to retarget the input layout while the ILT flow does support skew edges input by tool design and does not need any retargeting step before OPC. We will compare these two flows on various Si- Photonics waveguides from lithography quality, run time and MRC compliance of mask output. We will observe that ILT flow gives the best Edge Placement Error (EPE) and the lowest ripples along the devices. The ILT flow also takes into account the mask rules so that the generated mask is mask rule compliant (MRC). We will also discuss the silicon wafer data where Si-Photonics devices are printed within the two different OPC flows at process window conditions. Finally, for both OPC flows, we will present the total OPC run time which is acceptable in an industrial environment.

Multiple exposure patterning is now a main-stream method used in the manufacturing of modern integrated circuits.¹ However, the overlay statistics of these multiple exposure schemes has not been well understood. Splitting levels into multiple exposures (2x, 3x, etc. patterning) has a quantifiable effect on how overlay metrology relates to overlay process assumptions and capability. In addition, overlay metrology strategies used to measure a current layer back to a layer exposed with multiple exposures can also misrepresent the true overlay error. In this paper we look statistically at the effect of multiple exposures on the actual overlay error and compare it to that measured with overlay metrology.

Process assumptions (PAs) typically document the requirements between a current layer and a prior layer.² With single exposure layers the process assumption for overlay error of a current layer to a prior layer could be set knowing an exposure tool’s on product overlay capability, error sources for the layers involved, maximum acceptable rework rate and yield-loss the fab was able to accept. For a current layer that minimizes back to a prior layer that was exposed with multiple exposures, there are new sources of error to understand and consider.³ Understanding how these process assumptions relate to the capability of simple single layer to single layer overlay is desirable. This paper takes a new approach to calculating these relationships by using image-placement error and population statistics. This is different than former methods discussed in the literature that look at “2nd order” overlay calculations. We show that base single layer to single layer process capability needs to be tighter than process assumption of a current layer minimizing back to multiple prior layers with the specific amount of tightening directly related to the mean overlay error between multipatterned layers. Because of this, mean overlay specifications have to be set appropriately at prior layers to match process assumptions. As an example, if a contact layer is split into two exposures, the mean translation error between the two exposures needs to be minimized for good metal to contact overlay. This paper will describe the exact controls needed based on the new statistical understanding.

Setting ground-rules based on overlay PAs that are correctly determined, using the image placement and population statistics, is critical. Without the proper statistical understanding, it can be concluded that single layer to single layer overlay capability cannot support a technology using multiple exposures, resulting in increased die areas as ground-rules are relaxed for 2^nd order calculations incorrectly applied to the problem. Of course, the opposite is true if control of the mean overlay error of prior layers cannot be adequately controlled.

Through statistical analysis, we show that grouped overlay metrology of multiple exposures underestimates the true overlay error. This is due to the point-by-point averaging of layers that have been split into multiple exposures. Fortunately, the ratio between metrology and true overlay can be exactly calculated.

For the sub-20 nm DRAM nodes, wafer-to-wafer (W2W) variation is one of the major contributors to on-product overlay (OPO). One way to reduce the W2W variation is by applying overlay corrections on wafer level on top of per lot / per chuck corrections. These overlay corrections can e.g. be based on measurements of the OPO on the wafers to be corrected prior to rework and re-exposure. Measuring OPO on every wafer is not preferred due to the resulting metrology cost increase. Hence, wafers are typically assigned to a limited amount of groups, which are in turn assigned one common correction set for all the wafers within a particular group. The common corrections are obtained from measuring wafers from the respective groups. In this paper, we present results obtained by a different approach, where the wafer grouping is deduced from metrology data that is available prior to the exposure of the lot. Aim of this approach is to balance overlay control and OPO metrology effort. We experimentally demonstrated the benefit of our approach on one of the critical layers of a sub-20 nm DRAM product of SK hynix. The experiment was executed in a rework scenario, which involves exposing and measuring OPO on selected send-ahead (SAHD) wafers, their subsequent rework, and re-exposure of the full lot using per-group corrections derived from the OPO measurements of the SAHDs. The results of this experiment indicate a promising OPO improvement. Simulations performed on additional lots and for 3 additional layers confirm the validity of our results.

In advanced technological nodes, the photoresist absorbs light, which is reflected by underlying topography during optical lithography of implantation layers. Anti-reflective coating (ARC) helps to suppress the reflections, but ARC removal may damage transistors, not to mention its relatively high cost. Therefore ARC is usually not used, and topography modeling becomes obligatory for printing implantation shapes. Furthermore, presence of Fin Field Effect Transistors (FinFETs) makes modeling of non-uniform substrate reflections exceptionally challenging.

In realistic designs, the same implantation shape may be found in a vertical or in a rotated horizontal orientation. This creates two types of relationships between the critical dimension (CD) and FinFET, namely parallel to and perpendicular to the fins. The measurement data shows that CDs differ between these two orientations. This discrepancy is also revealed by our Rigorous Optical Topography simulator. Numerical experiments demonstrate that the shape orientation may introduce CD differences of up to 45 nm with a 248 nm illumination for 14 nm technology. These differences are highly dependent on the enclosure (distance between implantation shape and active area). One of the major causes of the differences is that in the parallel orientation the shape is facing solid sidewalls of fins, while the perpendicular oriented shape “sees” only perforated sidewalls of the fin structure, which reflect much less energy.

Meticulously stated numerical experiments helped us to thoroughly understand anisotropic behavior of CD measurement. This allowed us to more accurately account for FinFET-related topography effects in the compact implantation modeling for optical proximity corrections (OPC). This improvement is validated against wafer measurement data.

The final lithography accuracy is determined by what is known as the “on-product” performance, which includes product wafer-related errors and long-term stability. It is evident that on-product performance improvement is absolutely imperative now, and will become even more crucial in coming years. In order to meet customers’ future requirements, we have developed the next-generation lithography system focusing on wafer alignment advancements to improve onproduct performance.

This newly developed wafer alignment system will help customers achieve their aggressive next-generation manufacturing accuracy and productivity requirements. In this paper, we describe the details of the new wafer measurement system and provide supporting performance data.

Scanners in High-Volume-Manufacturing conditions will experience a large range of reticles that vary in reticle transmission and reticle diffraction characteristics. Especially under full production loads reticles will heat up due to the exposure light-load and as such experience thermo-mechanical deformations. The resulting reticle pattern distortion can be partially translated in a deteriorated overall system overlay. Due to the geometry of the reticle and exposure fields, these reticle thermal effects are in general barrel-shape distortions that can be well corrected with the available set of lens manipulators. Nevertheless node-over-node the residual overlay errors associated with thermo-mechanical reticle deformation needs further reduction since it contributes to the total onproduct overlay performance. To reduce overlay caused by reticle temperature drift, NXT1980Di includes an active cooling mechanism suppressing the reticle temperature changes during exposure significantly. Even though the reticle temperature excursions are well suppressed, residual intra-wafer overlay drift effect can still be observed. Before exposure of a wafer, reticle deformation is measured during reticle align using in-line alignment / image sensors (TIS or PARIS). This is enabled by adding alignment markers around the circumference of the image field on the reticle. The measured reticle deformations are then fed to the system control network and dynamically corrected for by making use of the available manipulators in the scanner and the projection lens. Wafer-by-wafer reticle distortion measurements are performed to accurately capture the transient dynamics present in reticle heating during normal production lots. A new version of Reticle Heating Feed-forward Control (RHC2) is introduced that uses reticle-heating-induced deformation measurements over time and exposure sequence information to calibrate reticle-deformation-predictionmodels. These models are based on thermo-mechanical models that simulate reticle deformation under various exposure conditions and are applied in-line to the exposures to reduce intra-wafer overlay drift effects.

Multi-patterning techniques with ArF immersion lithography continue to be extended into the 10 and 7 nm nodes. With increasingly challenging process control requirements (CD, overlay, edge placement error), the lithography and patterning tools need to find ways to minimize variation and maintain process margin to achieve high yields. This paper will describe new advances in light source technologies that can regain imaging margins by optimizing light source bandwidth settings in concert with OPC retargeting to take advantage of the contrast improvements^1,2 afforded by lower bandwidth. In addition to simulation studies reported previously^3,4, on-wafer measurements were collected showing the progressive improvements gained with lowering bandwidth on an existing mask as well as reoptimizing a mask to leverage this lower bandwidth setting. To fully leverage this capability, further improvements in bandwidth stability are going to be featured on a new ArF light source along with an integrated solution that allows the bandwidth target to be commanded by scanner recipe. This will allow lithographers to optimize layers that need further improvements in patterning by using lower bandwidth while continuing to run existing layers with standard, 300 fm bandwidth targets. With the introduction of a new DUV light source, this paper will also describe improvements that continue to reduce running costs in an effort to counteract the escalating costs of multi-patterning lithography.

Multiple patterning ArF immersion lithography has been expected as the promising technology to meet tighter leading edge device requirements. The most needed features for the next generation lasers are improvement of device yield, the prevention against rare resource shortage and the reduction of operational costs in multiple-patterning lithography [1] [2]. To support these requirements, GT65A provides the functions of tighter E95 bandwidth stability, lower E95 bandwidth and tunable E95 bandwidth to enhance chip yields [3] [4]. Furthermore, in the prevention against rare resource shortage and the reduction of operational costs, GT65A realizes helium-free operation in a line narrowing module (LNM) and the reduction of neon consumption in a chamber [5]. A faster actuator equipped with the movable lens enables shot average of E95 bandwidth stability to be within ±5 fm to more rapidly adjust laser beam wavefront. More stable spectral bandwidth stability leads to improve CD uniformity. New designed LNM realizes 200 fm of lower E95 bandwidth, because it suppresses thermal wavefront deformation in optical elements and mechanical components. Lower E95 bandwidth improves image contrast and enhances exposure latitude. The combination of a faster actuator and new LNM enables tunable E95 bandwidth to vary from 200 to 450 fm at less than time intervals of a wafer lot exchange, six seconds. This enhances imaging margins by optimizing E95 bandwidth of light sources according to individual scanners. New LNM additionally enables helium-free operation to lower E95 bandwidth in spite of nitrogen purge with higher refractive index variation to temperature. The employment of a new LNM can avoid helium supply risk and saves helium consumption of 80 kL/year/unit. Gas recycling system saves by about 92% of neon consumption in ArF laser. Similarly, the recycling system saves about 85% of neon consumption in KrF laser too. These functions with GT65A improve chip yield and process margins, and support sustainable high volume manufacturing (HVM).

ASML’s 300mm scanner-systems are built on the TWINSCAN (XT/NXT) platform and yield high productivity levels for dry as well as immersion litho-scanners. NXT:1980Di immersion scanners yield productivity levels as high as 275wph while maintaining the overlay accuracy. The NXT:1980Di can be equipped with a new leveling mode that results in a significant reduction of the time that is spent on measuring the wafer focus height map. In the new leveling mode the focus height map is measured employing the full width of the level sensor and thereby minimizing the number of leveling scans. In this paper we describe the implementation of the LIL-method in the TWINSCAN platform design. Here, we report on the focus / leveling performance for both test as well as customer product wafers, and present a productivity outlook on the performance gain for a selected set of exposure use-cases.

The Global 450mm Consortium (G450C) has completed its 5th year of developing and evaluating manufacturing 450mm tool sets. This paper focuses on how the lithography cell resolution performance has progressed from tool acceptance to current day. Initial data will be shown as well as the iterative and final data following process and equipment improvements that have been implemented over the course of the G450C program.

This paper will demonstrate both line/space and contact hole Critical Dimension Uniformity (CDU), one of the key indicators of resolution performance, as well as process window performance on multiple masks and resist processes. The CDU performance shows significant improvement after three main factors were implemented: custom-made photoresist, track process optimization, and Nikon Turnkey CDU Master software application. It will be demonstrated that with the implementation of optimized photoresist, Post Exposure bake (PEB) tuning and CDU Master correction that CDU results of <1nm 3σ may be achieved on 450mm wafers. The final CDU results for contact hole and line/space will be compared to 300mm production tools as well as the N7 and N10 expected requirements.

Besides a traditional 6% Attenuated Phase Shifting Mask (APSM), G450C litho also utilizes thin Opaque MoSi On Glass Mask (OMOG). Process window comparisons will be evaluated on both mask technologies for all of the resist processes. In addition to the test masks, G450C completed the design of a three layer mask set with resist based Optical Proximity Correction (OPC) modeling and gathered “on product” CDU performance on a Back End Of Line (BEOL) metal stack.

In the process nodes of 10nm and below, the patterning complexity, along with multiple pattern processing and the advance materials required, has in turn resulted in a need to optimize wafer alignment mark simulation capabilities in order to achieve the required precision and accuracy for wafer alignment performance.

ASML’s Design for Control (D4C) application for wafer alignment mark design has been extended to support the computational prediction of alignment mark performance for the latest alignment sensor on the TwinScan NXT:1980Di platform and beyond. Additional new simulation functionality will also be introduced to enable aberration sensitivity matching between the alignment mark and the device cell patterns. As a result, the design of more robust alignment marks is achieved, extending simulation capabilities for the design of wafer alignment marks and the recommendation of alignment recipe settings.

Accurate prediction of resist profile has become more important as technology node shrinks. Non-ideal resist profiles due to low image contrast and small depth of focus affect etch resistance and post-etch result. Therefore, accurate prediction of resist profile is important in lithographic hotspot verification. Standard approaches based on a single- or multiple-2D image simulation are not accurate, and rigorous resist simulation is too time consuming to apply to full-chip. We propose a new approach of resist profile modeling through machine learning (ML) technique. A position of interest are characterized by some geometric and optical parameters extracted from surroundings near the position. The parameters are then submitted to an artificial neural network (ANN) that outputs predicted value of resist height. The new resist 3D model is implemented in commercial OPC tool and demonstrated using 10nm technology metal layer.

As the fin based field effect transistors (Fin-FET) emerge, the device structure is changed from two dimensional to three dimensional. Due to the existence of topography, the lithographic performance may be affected and, in most cases, becomes more complicated, especially in the ion implantation process after gate being constructed. In this paper, the various parameters that may have influence on the resist topography are being investigated, such as the density, height, and corner rounding of the fin structures, the height, and the corner rounding of the gates, etc. Theoretical analysis shows that the resist image intensity among the fins and gates can be improved by increasing the thickness of the oxide on the edge of the gate. Following the above theoretical analysis, a method for lithographic performance improvement with the existence of resist topography is proposed. The method is demonstrated from the simulations with the lithography simulator PROLITH. With an optimal thickness of oxide on the surface of gate, the residual resist in the topography after development will be removed thoroughly. Compared with other methods, the proposed method requires neither a specific system setup nor an additional etch process, which is a tremendous cost-saving in mass production.

Laser interference lithography (LIL) is a maskless lithography technique with many advantages such as simple optical design, low cost, maskless, infinite depth of focus, and large area patterning with single exposure. Compare to the tradition optical lithography, LIL is very suitable for applications which need periodic nanostructure, such as grating, light-emitting diode (LED), photonic crystals, etc. However, due to the principle of LIL, the exposure result is very sensitive to the light source and the environment vibration. Defects which perpendicular or parallel to the grating occurs when the LIL system is effect by the environment vibration. The reason that cause this defect is Moiré fringe. When the periodic structure is fabricated in an environment with vibration source, the grating structure will have a small angle rotational vibration and the Moiré fringe defect is formed. In order to eliminate the Moiré fringe defect, this paper developed a new LIL system with chopper and accelerometer. The accelerometer can measure the vibration frequency. And by setting the chopper frequency equal to the vibration frequency, the Moiré fringe defects can be eliminate. In this paper, we use a piezo stage to generate a stable vibration source with tunable frequency. In this way, we can produce a repeatable Moiré fringe defect. By setting the chopper frequency equal to the stage vibration frequency, the Moiré fringe defect can be eliminate. And we successfully fabricated large area periodic structure without any vibration defects. The periodic structure is 360nm pitch and the area is 2x3 cm² .

The optical proximity correction (OPC) systematically adds the bias with respect to the designs to the mask, correcting the proximity effects associated with sub-wavelength features. Due to the complex nature of main features of the circuits, even a carefully tuned OPC recipe can yield thousands of weak points for each tape-out. Some of these weak points require manual fixings which might demand considerable amount of effects from engineers. It has been found that for different tape-outs, the resulting OPC patterns that require manual fixings share quite a lot commonalities or are even the same. Repeatedly performing manual fixings for the same type of weak points for different tape-outs presents a waste of human efforts. We therefore constructed a pattern matching library for these types of weak points. At the very of beginning of an OPC recipe, the design patterns of these types of weak points are used to scan the whole chip and find the same patterns. Then, the pre-calculated OPC and SB (scattering bar) layers are pasted to the relevant positions. The pasted patterns will be kept fixed and serve as boundary condition for the subsequent model-based OPC. The final resulting OPC layer will be free of those types of weak points that require manual fixings.

ArF immersion lithography is still a key candidate below 10nm node. Many challenges should be overcome when CD shrinks to such a tiny size. In the whole manufacturing flow, triple patterning (TP) is an important process. TP decomposition is used to decompose customers’ layout into three individual masks. Each of the decomposed masks can be imaged in a single exposure. Although the TP decomposition method is fully studied, rare research is focused on the influence of decomposition result on other processes, such as lithography, OPC (Optical Proximity correction), etch, etc. Thus, a decomposition result that is unfriendly to other processes may appear. In this paper, we propose a lithography and OPC friendly triple patterning decomposition method. The decomposition is classified into critical decomposition and optional decompositions. The critical decomposition is applied for pitches which are smaller than the minimum pitch of single exposure. The optional decomposition is firstly applied for pitches which are in the range of forbidden pitch, and then applied for pitches in the other ranges. The critical decomposition is assigned the highest priority, and the optional decomposition for the forbidden pitch is assigned the second highest priority, the decomposition for other pitches are assigned lower priorities. The balance process is also improved correspondingly. The results show the number of forbidden pitch can be reduced by 10.8% at most. In addition, the proposed method can be easily extended to suitable for other multiple patterning processes. And the idea of assigning different priorities in the decomposition can be also used for process optimization further.

The critical dimension(CD) is main factor to determine the line width of semiconductor equipment fabricating ability for the smallest line width of produced electronic components. Modulation transfer function(MTF) has been popularly used to evaluation the optical system, due to the contrast of each line-pair in dimension analytically, however, while the light source is coherent or near coherent for the small dimension near the optical diffraction limit, the MTF is hard to achieve consistently. The study of ultra-violet partial coherence modulation transfer function is to calculate the 1-D and 2-D the line with anoptical design program, to estimate the MTF near the size of diffraction limit. It provides fabricating parameter for a 1-to-1 TSV lithographic system. By applying partial coherence analysis, the optimized relative numerical aperture (RNA) has found. As the system is built, the optimized performance should be expected.

Source Optimization is a key techniques to enhance the process window in ArF 193i-nm lithography process. This paper proposes a source optimization algorithm combining metaheuristic-based binary ant colony source optimization (BACO) and an artificial neural network (ANN). The purpose of this study is to establish the optimal freeform source for improving the process window of the critical patterns and maintaining the quality of aerial images. The source plane is pixelated and divided into 25 sectors. In this study, a set of the input data for training the ANN includes the pattern edge contours resulting from the various process conditions with respect to each searching agent at each iteration. The trained ANN selects sectors with effective pixel sources illuminating the target pattern to enhance the aerial image quality and improve the process window. The combination of the B-ACO and ANN methods decreases the searching space and speed up the convergence of the B-ACO. PROLITHTM (KLA-Tencor) is used to calculate the aerial image when using the optimized freeform source. The developed algorithm is tested using the 17 clips of 1D line/space pattern with various line widths, pitches and line orientations. The testing pattern includes nine horizontal line features and eight vertical line features. The minimum line width is 40 nm with a pitch of 80nm, and the maximum linewidth is 120nm with a pitch of 500nm. An optimized freeform source is simultaneously constructed for these 17 clips. The imaging performance for these 17 clips is presented.