28 March 2017 Interlayer verification methodology for multi-patterning processes
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Abstract
Various multi-patterning processes with associated design methodologies have been deployed to address patterning challenges of ArFi and alternate solutions such as EUV, DSA or nanoimprint. Process variability prediction through compact models is sometimes limited to those multipatterning processes used to compose single final target. We may call those sequential processes as representative module for design target layer which is not clearly derived from single litho-etch process but derived from the interaction between various layers. Key challenges for extending multiple pattering are managing design and tolerance variation in multiple pattering steps with proper restrictions, and visualizing interlayer errors (w/ bridge & pinch and overlap). Additionally,visualization of final target layers and intermediate layers is important for process/design engineers.

We will demonstrate verification flows for different process modules to verify the failure mechanisms and to aid in visualization, then judge the areas for improvement with existing model based solutions. Then we will also try to investigate possible area for development of accurate residual error prediction from compact models as those errors are accumulated from multiple process effects into final CD measurement from design target layers. This may lead to new dimensions of modeling process effects we’ve never considered because those signatures were lumped between processes to processes.
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Sunwook Jung, Sunwook Jung, Sejin Park, Sejin Park, Jungmin Kim, Jungmin Kim, Jinhee Kim, Jinhee Kim, John Sturtevant, John Sturtevant, } "Interlayer verification methodology for multi-patterning processes", Proc. SPIE 10147, Optical Microlithography XXX, 101470J (28 March 2017); doi: 10.1117/12.2258356; https://doi.org/10.1117/12.2258356
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