30 March 2017 Computational scanner wafer mark alignment
Author Affiliations +
In the process nodes of 10nm and below, the patterning complexity, along with multiple pattern processing and the advance materials required, has in turn resulted in a need to optimize wafer alignment mark simulation capabilities in order to achieve the required precision and accuracy for wafer alignment performance.

ASML’s Design for Control (D4C) application for wafer alignment mark design has been extended to support the computational prediction of alignment mark performance for the latest alignment sensor on the TwinScan NXT:1980Di platform and beyond. Additional new simulation functionality will also be introduced to enable aberration sensitivity matching between the alignment mark and the device cell patterns. As a result, the design of more robust alignment marks is achieved, extending simulation capabilities for the design of wafer alignment marks and the recommendation of alignment recipe settings.
© (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Boris Menchtchikov, Boris Menchtchikov, Robert Socha, Robert Socha, Sudharshanan Raghunathan, Sudharshanan Raghunathan, Irina Lyulina, Irina Lyulina, Hielke Schoonewelle, Hielke Schoonewelle, Patrick Tinnemans, Patrick Tinnemans, Paul Tuffy, Paul Tuffy, Philippe Leray, Philippe Leray, Christiane Jehoul, Christiane Jehoul, } "Computational scanner wafer mark alignment", Proc. SPIE 10147, Optical Microlithography XXX, 101471C (30 March 2017); doi: 10.1117/12.2259750; https://doi.org/10.1117/12.2259750

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