Proceedings Volume 10148 is from: Logo
Feb 26 - Mar 2 2017
San Jose, California, United States
Front Matter: Volume 10148
Proc. SPIE 10148, Front Matter: Volume 10148, 1014801(2 May 2017);doi: 10.1117/12.2277800
Keynote Session
Proc. SPIE 10148, Low track height standard-cells enable high-placement density and low-BEOL cost (Conference Presentation), 1014803();doi: 10.1117/12.2257961
Proc. SPIE 10148, Optimization of self-aligned double patterning (SADP)-compliant layout designs using pattern matching for sub-20nm metal routing, 1014804(30 March 2017);doi: 10.1117/12.2258061
Physical Design Analytics and Machine Learning
Proc. SPIE 10148, Pattern-based analytics to estimate and track yield risk of designs down to 7nm, 1014805(30 March 2017);doi: 10.1117/12.2262363
Proc. SPIE 10148, Redundant via insertion in self-aligned double patterning, 1014806(28 March 2017);doi: 10.1117/12.2258036
Proc. SPIE 10148, Imbalance aware lithography hotspot detection: a deep learning approach, 1014807(28 March 2017);doi: 10.1117/12.2258374
Proc. SPIE 10148, Optimization of complex high-dimensional layout configurations for IC physical designs using graph search, data analytics, and machine learning, 1014808(3 April 2017);doi: 10.1117/12.2262146
Design Interactions with Lithography: Joint Session with Conferences 10147 and 10148
Proc. SPIE 10148, Cost effective solution using inverse lithography OPC for DRAM random contact layer, 1014809(4 April 2017);doi: 10.1117/12.2257857
Proc. SPIE 10148, SOCS based post-layout optimization for multiple patterns with light interference prediction, 101480A(30 March 2017);doi: 10.1117/12.2260091
Directed Self-Assembly and Design Co-optimization
Proc. SPIE 10148, Design technology co-optimization (DTCO) study on self-aligned-via (SAV) with Lamella DSA for sub-7 nm technology, 101480B(30 March 2017);doi: 10.1117/12.2258056
Proc. SPIE 10148, Efficient DSA-DP hybrid lithography conflict detection and guiding template assignment, 101480C(28 March 2017);doi: 10.1117/12.2258156
Proc. SPIE 10148, Technology path-finding for directed self-assembly for via layers, 101480D(28 March 2017);doi: 10.1117/12.2257821
Proc. SPIE 10148, Density driven placement of sub-DSA resolution assistant features (SDRAFs), 101480E(28 March 2017);doi: 10.1117/12.2257954
Proc. SPIE 10148, Exploiting regularity: breakthroughs in sub-7nm place-and-route, 101480F(28 March 2017);doi: 10.1117/12.2259981
Proc. SPIE 10148, The effect of patterning options on embedded memory cells in logic technologies at iN10 and iN7, 101480G(28 March 2017);doi: 10.1117/12.2255089
Proc. SPIE 10148, Design intent optimization at the beyond 7nm node: the intersection of DTCO and EUVL stochastic mitigation techniques, 101480H(30 March 2017);doi: 10.1117/12.2260865
Proc. SPIE 10148, Identification and sensitivity analysis of a correlated ground rule system (design arc), 101480I(4 April 2017);doi: 10.1117/12.2258002
Proc. SPIE 10148, Large marginal 2D self-aligned via patterning for sub-5nm technology, 101480J(28 March 2017);doi: 10.1117/12.2257924
Proc. SPIE 10148, Routability enhancement through unidirectional standard cells with floating metal-2, 101480K(28 March 2017);doi: 10.1117/12.2258010
Design Interactions with Metrology: Joint Session with Conferences 10148 and 10145
Proc. SPIE 10148, Wafer hot spot identification through advanced photomask characterization techniques: part 2, 101480L(28 March 2017);doi: 10.1117/12.2257676
Proc. SPIE 10148, Line-edge quality optimization of electron beam resist for high-throughput character projection exposure utilizing atomic force microscope analysis, 101480M(4 April 2017);doi: 10.1117/12.2257976
Electrical Design for Manufacturability
Proc. SPIE 10148, Quantifying electrical impacts on redundant wire insertion in 7nm unidirectional designs, 101480N(3 April 2017);doi: 10.1117/12.2261588
Proc. SPIE 10148, Selection of airgap layers for circuit timing optimization, 101480O(28 March 2017);doi: 10.1117/12.2258034
Proc. SPIE 10148, Systematic analysis of the timing and power impact of pure lines and cuts routing for multiple patterning, 101480P(28 March 2017);doi: 10.1117/12.2258085
Proc. SPIE 10148, Cutting-edge CMP modeling for front-end-of-line (FEOL) and full stack hotspot detection for advanced technologies, 101480Q(28 March 2017);doi: 10.1117/12.2262076
Proc. SPIE 10148, Stitch overlap via coloring technique enables maskless via, 101480R(28 March 2017);doi: 10.1117/12.2258640
Methodologies for Design-Process-Technology-Co-optimization
Proc. SPIE 10148, Early stage hot spot analysis through standard cell base random pattern generation, 101480S(4 April 2017);doi: 10.1117/12.2257830
Proc. SPIE 10148, Design space sampling using hierarchical clustering of patterns on a full chip, 101480T(28 March 2017);doi: 10.1117/12.2257988
Proc. SPIE 10148, A fuzzy pattern matching method based on graph kernel for lithography hotspot detection, 101480U(28 March 2017);doi: 10.1117/12.2257654
Proc. SPIE 10148, Design and pitch scaling for affordable node transition and EUV insertion scenario, 101480V(26 April 2017);doi: 10.1117/12.2257885
Proc. SPIE 10148, Transforming information from silicon testing and design characterization into numerical data sets for yield learning, 101480W(30 March 2017);doi: 10.1117/12.2259950
Poster Session
Proc. SPIE 10148, A pattern-based design analysis method by using inline inspection data more efficiently, 101480X(28 March 2017);doi: 10.1117/12.2259936
Proc. SPIE 10148, Low track height standard cell design in iN7 using scaling boosters, 101480Y(4 April 2017);doi: 10.1117/12.2257658
Proc. SPIE 10148, Design space analysis of novel interconnect constructs for 22nm FDX technology, 101480Z(30 March 2017);doi: 10.1117/12.2258668
Proc. SPIE 10148, IR-drop analysis for validating power grids and standard cell architectures in sub-10nm node designs, 1014810(28 March 2017);doi: 10.1117/12.2258340
Proc. SPIE 10148, A random generation approach to pattern library creation for full chip lithographic simulation, 1014811(4 April 2017);doi: 10.1117/12.2258133
Proc. SPIE 10148, Gate tie-down construct in the 22FDX technology: a silicon-based method for layout optimization, 1014812(28 March 2017);doi: 10.1117/12.2258453
Proc. SPIE 10148, The new OPC method for obtaining the stability of MBAF OPC, 1014813(28 March 2017);doi: 10.1117/12.2257872
Proc. SPIE 10148, User-friendly design approach for analog layout design, 1014814(28 March 2017);doi: 10.1117/12.2258203
Proc. SPIE 10148, A fast process development flow by applying design technology co-optimization, 1014815(28 March 2017);doi: 10.1117/12.2257973
Proc. SPIE 10148, A novel approach of ensuring layout regularity correct by construction in advanced technologies, 1014816(28 March 2017);doi: 10.1117/12.2257552
Proc. SPIE 10148, Hotspots fixing flow in NTD process by using DTCO methodology at 10nm metal 1 layer, 1014817(28 March 2017);doi: 10.1117/12.2257786
Proc. SPIE 10148, Stitching-aware in-design DPT auto fixing for sub-20nm logic devices, 1014818(28 March 2017);doi: 10.1117/12.2262836
Proc. SPIE 10148, Process weakness assessment by profiling all incoming design components, 1014819(30 March 2017);doi: 10.1117/12.2260311
Proc. SPIE 10148, Using pattern matching to increase performance in hotspot fixing flows, 101481A(28 March 2017);doi: 10.1117/12.2258095
Proc. SPIE 10148, Litho hotspots fixing using model based algorithm, 101481B(4 April 2017);doi: 10.1117/12.2257630
Proc. SPIE 10148, Using design differentiating methods to find suspect design patterns which cause failure, 101481C(30 March 2017);doi: 10.1117/12.2259947
Proc. SPIE 10148, Electrical failure debug using interlayer profiling method, 101481D(30 March 2017);doi: 10.1117/12.2259944
Proc. SPIE 10148, A fast and efficient method for device level layout analysis, 101481E(30 March 2017);doi: 10.1117/12.2257895
Proc. SPIE 10148, Pattern database applications from design to manufacturing, 101481F(30 March 2017);doi: 10.1117/12.2259934
Proc. SPIE 10148, Enhancing manufacturability of standard cells by using DTCO methodology, 101481G(4 April 2017);doi: 10.1117/12.2263178
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