This new integrated flow consists of applying ILT to the difficult core region and traditional rule-based assist features (RBAFs) with OPC to the peripheral region of a DRAM contact layer. Comparisons of wafer results between the ILT process and the non-ILT process showed the lithographic benefits of ILT and its ability to enable a robust single patterning process for this low-k1 device layer. Advanced modeling with a negative tone develop (NTD) process achieved the accuracy levels needed for ILT to control feature shapes through dose and focus. Details of these afore mentioned results will be described in the paper.
ACCESS THE FULL ARTICLE
Jinhyuck Jun, Jaehee Hwang, Jaeseung Choi, Seyoung Oh, Chanha Park, Hyunjo Yang, Thuc Dam, Munhoe Do, Dong Chan Lee, Guangming Xiao, Jung-Hoe Choi, Kevin Lucas, "Cost effective solution using inverse lithography OPC for DRAM random contact layer," Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014809 (4 April 2017);