4 April 2017 Cost effective solution using inverse lithography OPC for DRAM random contact layer
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Abstract
Many different advanced devices and design layers currently employ double patterning technology (DPT) as a means to overcome lithographic and OPC limitations at low k1 values. Certainly device layers with k1 value below 0.25 require DPT or other pitch splitting methodologies. DPT has also been used to improve patterning of certain device layers with k1 values slightly above 0.25, due to the difficulty of achieving sufficient pattern fidelity with only a single exposure. Unfortunately, this broad adoption of DPT also came with a significant increase in patterning process cost. In this paper, we discuss the development of a single patterning technology process using an integrated Inverse Lithography Technology (ILT) flow for mask synthesis. A single pattering technology flow will reduce the manufacturing cost for a k1 > 0.25 full chip random contact layer in a memory device by replacing the more expensive DPT process with ILT flow, while also maintaining good lithographic production quality and manufacturable OPC/RET production metrics.

This new integrated flow consists of applying ILT to the difficult core region and traditional rule-based assist features (RBAFs) with OPC to the peripheral region of a DRAM contact layer. Comparisons of wafer results between the ILT process and the non-ILT process showed the lithographic benefits of ILT and its ability to enable a robust single patterning process for this low-k1 device layer. Advanced modeling with a negative tone develop (NTD) process achieved the accuracy levels needed for ILT to control feature shapes through dose and focus. Details of these afore mentioned results will be described in the paper.
Conference Presentation
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Jinhyuck Jun, Jaehee Hwang, Jaeseung Choi, Seyoung Oh, Chanha Park, Hyunjo Yang, Thuc Dam, Munhoe Do, Dong Chan Lee, Guangming Xiao, Jung-Hoe Choi, Kevin Lucas, "Cost effective solution using inverse lithography OPC for DRAM random contact layer", Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014809 (4 April 2017); doi: 10.1117/12.2257857; https://doi.org/10.1117/12.2257857
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