28 March 2017 The effect of patterning options on embedded memory cells in logic technologies at iN10 and iN7
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Abstract
Static Random Access Memory (SRAM) cells are used together with logic standard cells as the benchmark to develop the process flow for new logic technologies. In order to achieve successful integration of Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) as area efficient higher level embedded cache, it also needs to be included as a benchmark. The simple cell structure of STT-MRAM brings extra patterning challenges to achieve high density. The two memory types are compared in terms of minimum area and critical design rules in both the iN10 and iN7 node, with an extra focus on patterning options in iN7. Both the use of Self-Aligned Quadruple Patterning (SAQP) mandrel and spacer engineering, as well as multi-level via’s are explored. These patterning options result in large area gains for the STT-MRAM cell and moreover determine which cell variant is the smallest.
Conference Presentation
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Raf Appeltans, Raf Appeltans, Pieter Weckx, Pieter Weckx, Praveen Raghavan, Praveen Raghavan, Ryoung-Han Kim, Ryoung-Han Kim, Gouri Sankar Kar, Gouri Sankar Kar, Arnaud Furnémont, Arnaud Furnémont, Liesbet Van der Perre, Liesbet Van der Perre, Wim Dehaene, Wim Dehaene, } "The effect of patterning options on embedded memory cells in logic technologies at iN10 and iN7", Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480G (28 March 2017); doi: 10.1117/12.2255089; https://doi.org/10.1117/12.2255089
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