Large marginal 2D self-aligned via patterning for sub-5nm technology

Suhyeong Choi; Jae Uk Lee; Victor M. Blanco Carballo; Peter Debacker; Praveen Raghavan; Ryoung-Han Kim; Youngsoo Shin

doi:10.1117/12.2257924

28 March 2017 Large marginal 2D self-aligned via patterning for sub-5nm technology

Suhyeong Choi, Jae Uk Lee, Victor M. Blanco Carballo, Peter Debacker, Praveen Raghavan, Ryoung-Han Kim, Youngsoo Shin

Proceedings Volume 10148, Design-Process-Technology Co-optimization for Manufacturability XI; 101480J (2017) https://doi.org/10.1117/12.2257924
Event: SPIE Advanced Lithography, 2017, San Jose, California, United States

Abstract

Conventional via patterning which relies on immersion ArF (iArF) lithography and self-aligned via (SAV) becomes challenging in sub-7nm technology. EUV lithography (EUVL) is expected to achieve smaller feature patterning thanks to its short wave length, but edge placement error (EPE) margin remains as another bottleneck of pitch scaling; SAV can be aligned with metal on the top but not with the bottom of the via. Literary study shows previous work on 2D self-aligned via (2D SAV) which can be aligned with the both metals, but it cannot extend technology scaling beyond sub-5nm whose minimum metal pitch is expected as sub-20nm due to essential limitation of EPE margin. We propose large marginal 2D SAV which has three times large EPE margin than normal 2D SAV for extremely shrunk technology node (e.g. sub-5nm). Large marginal 2D SAV may allow further feature size scaling, but it requires four EUV masks. Therefore, we present two count reduction methods and corresponding mask decompositions and pattern re-targetings. Proposed re-targeted patterns are assessed by source mask optimization (SMO) in terms of maximum EPE and process variation band (PVB) width.

Citation Download Citation

Suhyeong Choi, Jae Uk Lee, Victor M. Blanco Carballo, Peter Debacker, Praveen Raghavan, Ryoung-Han Kim, and Youngsoo Shin "Large marginal 2D self-aligned via patterning for sub-5nm technology", Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480J (28 March 2017); https://doi.org/10.1117/12.2257924

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