4 April 2017 Early stage hot spot analysis through standard cell base random pattern generation
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Abstract
Due to limited availability of DRC clean patterns during the process and RET recipe development, OPC recipes are not tested with high pattern coverage. Various kinds of pattern can help OPC engineer to detect sensitive patterns to lithographic effects. Random pattern generation is needed to secure robust OPC recipe. However, simple random patterns without considering real product layout style can’t cover patterning hotspot in production levels. It is not effective to use them for OPC optimization thus it is important to generate random patterns similar to real product patterns. This paper presents a strategy for generating random patterns based on design architecture information and preventing hotspot in early process development stage through a tool called Layout Schema Generator (LSG). Using LSG, we generate standard cell based on random patterns reflecting real design cell structure – fin pitch, gate pitch and cell height. The output standard cells from LSG are applied to an analysis methodology to assess their hotspot severity by assigning a score according to their optical image parameters - NILS, MEEF, %PV band and thus potential hotspots can be defined by determining their ranking. This flow is demonstrated on Samsung 7nm technology optimizing OPC recipe and early enough in the process avoiding using problematic patterns.
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Joong-Won Jeon, Jaewan Song, Jeong-Lim Kim, Seongyul Park, Seung-Hune Yang, Sooryong Lee, Hokyu Kang, Kareem Madkour, Wael ElManhawy, SeungJo Lee, Joe Kwan, "Early stage hot spot analysis through standard cell base random pattern generation", Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480S (4 April 2017); doi: 10.1117/12.2257830; https://doi.org/10.1117/12.2257830
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