28 March 2017 Gate tie-down construct in the 22FDX technology: a silicon-based method for layout optimization
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Abstract
In order to allow competitive and low-cost designs in the 22nm FD-SOI technology 22FDX™, novel Middle-of-Line (MOL) constructs have been specifically enabled. The Gate Tie-Down (or “continuous RX”) construct allows an optimal device performance without loss of area. A method for a silicon-based evaluation and optimization of the Gate Tie-Down construct is presented here. We discuss the main design-process failure modes, their severity and the risk mitigation options. A full-factorial Design of Experiment used for the construct validation is presented and analyzed. Two critical failure modes are isolated and discussed. As a final step, the optimized design is validated over a much larger number of occurrences, showing a robust 4-sigma manufacturing design margin.
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B. Ramadout, D. Wehella-Gamage, T. Staiger, H.-P. Moll, T.-Guha Neogi, "Gate tie-down construct in the 22FDX technology: a silicon-based method for layout optimization", Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014812 (28 March 2017); doi: 10.1117/12.2258453; https://doi.org/10.1117/12.2258453
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