28 March 2017 User-friendly design approach for analog layout design
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Analog circuits are sensitives to the changes in the layout environment conditions, manufacturing processes, and variations. This paper presents analog verification flow with five types of analogfocused layout constraint checks to assist engineers in identifying any potential device mismatch and layout drawing mistakes. Compared to several solutions, our approach only requires layout design, which is sufficient to recognize all the matched devices. Our approach simplifies the data preparation and allows seamless integration into the layout environment with minimum disruption to the custom layout flow. Our user-friendly analog verification flow provides the engineer with more confident with their layouts quality.
© (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yongfu Li, Yongfu Li, Zhao Chuan Lee, Zhao Chuan Lee, Vikas Tripathi, Vikas Tripathi, Valerio Perez, Valerio Perez, Yoong Seang Ong, Yoong Seang Ong, Chiu Wing Hui, Chiu Wing Hui, } "User-friendly design approach for analog layout design", Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014814 (28 March 2017); doi: 10.1117/12.2258203; https://doi.org/10.1117/12.2258203

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