In this paper, we present the Stitching-Aware In-design DPT Auto Fixing method for better fixing rates and smaller chip design. The previous In-design DPT Auto Fixing method detected all DPT odd-cycles and tried to remove oddcycles by increasing the adjacent space. As the metal congestions increase in the newer technology nodes, the older Auto Fixing method has limitations to increase the adjacent space between routing metals. Consequently, the auto fixing rate of older method gets worse with the introduction of the smaller design rules. With DPT stitching enablement at In-design DRC checking procedure, the new Stitching-Aware DPT Auto Fixing method detects the most critical odd-cycles and revolve the odd-cycles automatically. The accuracy of new flow ensures better usage of space in the congested areas, and helps design more smaller chips.
By applying the Stitching-Aware DPT Auto Fixing method to sub-20nm logic devices, we can confirm that the auto fixing rate is improved by ~2X compared with auto fixing without stitching. Additionally, by developing the better heuristic algorithm and flow for DPT stitching, we can get DPT compliant layout with the acceptable design TATs.