Presentation
27 April 2017 Impact of materials engineering on edge placement error (Conference Presentation)
Regina Freed, Uday Mitra, Ying Zhang
Author Affiliations +
Abstract
Transistor scaling has transitioned from wavelength scaling to multi-patterning techniques, due to the resolution limits of immersion of immersion lithography. Deposition and etch have enabled scaling in the by means of SADP and SAQP. Spacer based patterning enables extremely small linewidths, sufficient for several future generations of transistors. However, aligning layers in Z-direction, as well as aligning cut and via patterning layers, is becoming a road-block due to global and local feature variation and fidelity. This presentation will highlight the impact of deposition and etch on this feature alignment (EPE) and illustrate potential paths toward lowering EPE using material engineering.
Conference Presentation
© (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Regina Freed, Uday Mitra, and Ying Zhang "Impact of materials engineering on edge placement error (Conference Presentation)", Proc. SPIE 10149, Advanced Etch Technology for Nanopatterning VI, 1014905 (27 April 2017); https://doi.org/10.1117/12.2261107
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KEYWORDS
Etching

Error analysis

Optical lithography

Transistors

Immersion lithography

Current controlled current source

Nanostructures

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