4 April 2017 Self-aligned quadruple patterning using spacer on spacer integration optimization for N5
Author Affiliations +
Abstract
To meet scaling requirements, the semiconductor industry has extended 193nm immersion lithography beyond its minimum pitch limitation using multiple patterning schemes such as self-aligned double patterning, self-aligned quadruple patterning and litho-etch / litho etch iterations. Those techniques have been declined in numerous options in the last few years. Spacer on spacer pitch splitting integration has been proven to show multiple advantages compared to conventional pitch splitting approach. Reducing the number of pattern transfer steps associated with sacrificial layers resulted in significant decrease of cost and an overall simplification of the double pitch split technique.

While demonstrating attractive aspects, SAQP spacer on spacer flow brings challenges of its own. Namely, material set selections and etch chemistry development for adequate selectivities, mandrel shape and spacer shape engineering to improve edge placement error (EPE). In this paper we follow up and extend upon our previous learning and proceed into more details on the robustness of the integration in regards to final pattern transfer and full wafer critical dimension uniformity. Furthermore, since the number of intermediate steps is reduced, one will expect improved uniformity and pitch walking control. This assertion will be verified through a thorough pitch walking analysis.
Conference Presentation
© (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Sophie Thibaut, Angélique Raley, Nihar Mohanty, Subhadeep Kal, Eric Liu, Akiteru Ko, David O'Meara, Kandabara Tapily, Peter Biolsi, "Self-aligned quadruple patterning using spacer on spacer integration optimization for N5", Proc. SPIE 10149, Advanced Etch Technology for Nanopatterning VI, 101490I (4 April 2017); doi: 10.1117/12.2258173; https://doi.org/10.1117/12.2258173
PROCEEDINGS
11 PAGES + PRESENTATION

SHARE
RELATED CONTENT

Analyzing block placement errors in SADP patterning
Proceedings of SPIE (March 21 2016)
Evaluation of ALE processes for patterning
Proceedings of SPIE (March 23 2016)
Etch challenges for 1xnm NAND flash
Proceedings of SPIE (March 16 2012)
Sidewall spacer quadruple patterning for 15nm half-pitch
Proceedings of SPIE (March 22 2011)

Back to Top