Paper
21 March 2017 The application of advanced pulsed plasma in Fin etch loading improvement
Fang-Yuan Xiao, Qiu-Hua Han, Hai-Yang Zhang
Author Affiliations +
Abstract
Following Moore’s law, integrated circuit requires scaling gate length to 14nm and beyond. To enable such gate-length scaling, finFETs have widely replaced planar metal-oxide-semiconductor field-effect transistors (MOSFETs) due to its special 3D structure could provide larger effective channel width and better short channel controllability. However, Fin critical dimension (CD) and profile variation between dense and ISO fin in a conventional etch process can introduce additional device degradation. Therefore, rigorous process loading control in reactive ion etch (RIE) becomes more critical. This paper mainly focused on self-aligned double patterning mandrel etch and fin etch by using advanced pulsed plasma to deliver a well-loading fin.
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Fang-Yuan Xiao, Qiu-Hua Han, and Hai-Yang Zhang "The application of advanced pulsed plasma in Fin etch loading improvement", Proc. SPIE 10149, Advanced Etch Technology for Nanopatterning VI, 101490Z (21 March 2017); https://doi.org/10.1117/12.2266539
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KEYWORDS
Etching

Plasma

Plasma etching

Focus stacking software

Ions

Polymers

Critical dimension metrology

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