19 October 2016 A 256×256 low-light-level CMOS imaging sensor with digital CDS
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Proceedings Volume 10155, Optical Measurement Technology and Instrumentation; 101552T (2016) https://doi.org/10.1117/12.2247213
Event: International Symposium on Optoelectronic Technology and Application 2016, 2016, Beijing, China
In order to achieve high sensitivity for low-light-level CMOS image sensors (CIS), a capacitive transimpedance amplifier (CTIA) pixel circuit with a small integration capacitor is used. As the pixel and the column area are highly constrained, it is difficult to achieve analog correlated double sampling (CDS) to remove the noise for low-light-level CIS. So a digital CDS is adopted, which realizes the subtraction algorithm between the reset signal and pixel signal off-chip. The pixel reset noise and part of the column fixed-pattern noise (FPN) can be greatly reduced. A 256×256 CIS with CTIA array and digital CDS is implemented in the 0.35μm CMOS technology. The chip size is 7.7mm×6.75mm, and the pixel size is 15μm×15μm with a fill factor of 20.6%. The measured pixel noise is 24LSB with digital CDS in RMS value at dark condition, which shows 7.8× reduction compared to the image sensor without digital CDS. Running at 7fps, this low-light-level CIS can capture recognizable images with the illumination down to 0.1lux.
© (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Mei Zou, Mei Zou, Nan Chen, Nan Chen, Shengyou Zhong, Shengyou Zhong, Zhengfen Li, Zhengfen Li, Jicun Zhang, Jicun Zhang, Li-bin Yao, Li-bin Yao, } "A 256×256 low-light-level CMOS imaging sensor with digital CDS", Proc. SPIE 10155, Optical Measurement Technology and Instrumentation, 101552T (19 October 2016); doi: 10.1117/12.2247213; https://doi.org/10.1117/12.2247213

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