22 December 2016 Bipolar transistor in VESTIC technology: prototype
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Proceedings Volume 10175, Electron Technology Conference 2016; 101750E (2016) https://doi.org/10.1117/12.2260787
Event: Electron Technology Conference ELTE 2016, 2016, Wisla, Poland
VESTIC technology is an alternative for traditional CMOS technology. This paper presents first measurement data of prototypes of VES-BJT: bipolar transistors in VESTIC technology. The VES-BJT is a bipolar transistor on the SOI substrate with symmetric lateral structure and both emitter and collector made of polysilicon. The results indicate that VES-BJT can be a device with useful characteristics. Therefore, VESTIC technology has the potential to become a new BiCMOS-type technology with some unique properties.
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Piotr Mierzwiński, Wiesław Kuźmicz, Krzysztof Domański, Daniel Tomaszewski, Grzegorz Głuszko, "Bipolar transistor in VESTIC technology: prototype", Proc. SPIE 10175, Electron Technology Conference 2016, 101750E (22 December 2016); doi: 10.1117/12.2260787; https://doi.org/10.1117/12.2260787

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