22 December 2016 CMOS standard cells characterization for open defects for test pattern generation
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Proceedings Volume 10175, Electron Technology Conference 2016; 101750I (2016) https://doi.org/10.1117/12.2261887
Event: Electron Technology Conference ELTE 2016, 2016, Wisla, Poland
Abstract
This paper presents an extended method of CMOS standard cells characterization for defect based voltage testing. It allows to estimate the probabilities of physical open defects occurrences in a cell, describes its faulty behavior caused by the defects and finds the test sequences that detect those faults. Finally, the minimal set of test sequences is selected to cover all detectable faults and the optimal complex test sequence is constructed. Experimental results for cells from industrial standard cell library are presented as well.
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Andrzej Wielgus, Witold Pleskacz, "CMOS standard cells characterization for open defects for test pattern generation ", Proc. SPIE 10175, Electron Technology Conference 2016, 101750I (22 December 2016); doi: 10.1117/12.2261887; https://doi.org/10.1117/12.2261887
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