28 April 2017 An acceleration framework for synthetic aperture radar algorithms
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Abstract
Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, Field Programmable Gate Arrays (FPGAs) can be used to accelerate these kernels using hardware-based custom logic implementations. In this paper, we demonstrate a framework for algorithm acceleration. We used SAR as a case study to illustrate the potential for algorithm acceleration offered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show a linear speedup by adding reasonably small processing elements in Field Programmable Gate Array (FPGA) as opposed to using a software implementation running on a typical general purpose processor.
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Youngsoo Kim, Clay S. Gloster, Winser E. Alexander, "An acceleration framework for synthetic aperture radar algorithms", Proc. SPIE 10201, Algorithms for Synthetic Aperture Radar Imagery XXIV, 102010F (28 April 2017); doi: 10.1117/12.2261397; https://doi.org/10.1117/12.2261397
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