1 May 2017 Real-time depth processing for embedded platforms
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Obtaining depth information of a scene is an important requirement in many computer-vision and robotics applications. For embedded platforms, passive stereo systems have many advantages over their active counterparts (i.e. LiDAR, Infrared). They are power efficient, cheap, robust to lighting conditions and inherently synchronized to the RGB images of the scene. However, stereo depth estimation is a computationally expensive task that operates over large amounts of data. For embedded applications which are often constrained by power consumption, obtaining accurate results in real-time is a challenge. We demonstrate a computationally and memory efficient implementation of a stereo block-matching algorithm in FPGA. The computational core achieves a throughput of 577 fps at standard VGA resolution whilst consuming less than 3 Watts of power. The data is processed using an in-stream approach that minimizes memory-access bottlenecks and best matches the raster scan readout of modern digital image sensors.
© (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Oscar Rahnama, Oscar Rahnama, Aleksej Makarov, Aleksej Makarov, Philip Torr, Philip Torr, "Real-time depth processing for embedded platforms", Proc. SPIE 10223, Real-Time Image and Video Processing 2017, 102230N (1 May 2017); doi: 10.1117/12.2272504; https://doi.org/10.1117/12.2272504


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